Searched refs:isl (Results 1 - 25 of 59) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/
H A DMakefile.sources165 isl/isl.c \
166 isl/isl.h \
167 isl/isl_drm.c \
168 isl/isl_format.c \
169 isl/isl_genX_priv.h \
170 isl/isl_priv.h \
171 isl/isl_storage_image.c
174 isl/isl_gen
[all...]
H A DAndroid.isl.mk296 $(LOCAL_PATH)/isl/gen_format_layout.py \
297 $(LOCAL_PATH)/isl/isl_format_layout.csv
299 $(intermediates)/isl/isl_format_layout.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/isl/gen_format_layout.py
300 $(intermediates)/isl/isl_format_layout.c: PRIVATE_CSV := $(LOCAL_PATH)/isl/isl_format_layout.csv
301 $(intermediates)/isl/isl_format_layout.c: $(isl_format_layout_deps)
H A DAndroid.mk33 include $(LOCAL_PATH)/Android.isl.mk
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_image.c138 assert(surf->isl.size_B > 0); /* isl surface must be initialized */
142 surf->isl.alignment_B);
145 surf->offset = align_u32(image->size, surf->isl.alignment_B);
151 image->size = surf->offset + surf->isl.size_B;
152 image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
154 image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
156 surf->isl.alignment_B);
250 assert(image->planes[plane].aux_surface.isl.size_B > 0 &&
339 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
[all...]
H A DgenX_cmd_buffer.c253 if (iview->planes[0].isl.base_array_layer >=
255 iview->planes[0].isl.base_level)) {
290 if (isl_format_supports_ccs_e(&device->info, iview->planes[0].isl.format)) {
309 assert(iview->image->planes[0].aux_surface.isl.usage &
316 isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format);
318 isl_color_value_is_zero(clear_color, iview->planes[0].isl.format);
363 (iview->planes[0].isl.base_level > 0 ||
364 iview->planes[0].isl.base_array_layer > 0)) {
424 iview->planes[0].isl.format,
937 if (image->planes[plane].shadow_surface.isl
[all...]
H A Danv_dump.c444 iview->planes[plane].isl.base_level,
445 iview->planes[plane].isl.base_array_layer,
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_image.c312 /* isl surface must be initialized */
313 assert(surf->isl.size_B > 0);
316 surf->isl.size_B,
317 surf->isl.alignment_B,
558 &image->planes[plane].primary_surface.isl,
559 &image->planes[plane].aux_surface.isl);
564 &image->planes[plane].primary_surface.isl,
565 &image->planes[plane].aux_surface.isl)) {
599 &image->planes[plane].primary_surface.isl,
642 &image->planes[plane].primary_surface.isl,
[all...]
H A DgenX_cmd_buffer.c364 if (iview->planes[0].isl.base_array_layer >=
366 iview->planes[0].isl.base_level))
381 if (!isl_color_value_is_zero(clear_color, iview->planes[0].isl.format))
400 !isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format))
409 &iview->image->planes[0].primary_surface.isl,
410 &iview->planes[0].isl)) {
424 if (iview->planes[0].isl.base_level > 0 ||
425 iview->planes[0].isl.base_array_layer > 0) {
468 &iview->image->planes[0].primary_surface.isl,
470 iview->planes[0].isl
[all...]
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.1.2.rst78 - intel/isl: Add bounds-checking assertions in isl_format_get_layout
79 - intel/isl: Add bounds-checking assertions for the format_info table
H A D20.0.3.rst111 - isl: implement linear tiling row pitch requirement for display
112 - isl: properly filter supported display modifiers on Gen9+
113 - isl: only apply main surface ccs pitch constraint with CCS
114 - isl: drop min row pitch alignment when set by the driver
H A D17.1.5.rst66 - intel/isl: Use uint64_t to store total surface size
67 - intel/isl: Add the maximum surface size limit
H A D20.2.2.rst110 - intel/isl: Drop redundant unpack of unorm channels
111 - isl: Fix the aux-map encoding for D24_UNORM_X8
H A D21.1.8.rst55 - isl: drop left-over comment
H A D17.0.7.rst102 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
H A D13.0.5.rst145 - isl/formats: Only advertise sampling for A4B4G4R4 on Broadwell
161 - anv: don't require render target isl bit for depth/stencil surfaces
H A D21.1.1.rst131 - intel/isl: Add Wa_22011186057 to disable CCS on ADL GT2 A0
206 - isl: require hiz for depth surface in isl_surf_get_ccs_surf
H A D19.3.0.rst467 - intel/isl/icl: Use halign 8 instead of 4 hw workaround
1791 - intel/isl: Select Y-tiling for stencil on gen12
1792 - intel/isl: Add isl_aux_usage_has_ccs
1796 - intel/isl: Add new aux modes available on gen12
1797 - intel/isl/fill_state: Separate aux_mode handling from aux_surf
1798 - intel/isl: Update surf_fill_state for gen12
1799 - intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz
1942 - intel/isl: Build gen12 using gen11 code paths
1952 - intel/genxml,isl: Add gen12 render surface state changes
1953 - intel/genxml,isl
[all...]
H A D12.0.2.rst145 - isl: automake: use VISIBILITY_CFLAGS to restrict symbol visibility
234 - isl: Allow multisampled array textures
309 - isl: Fix assert on raw buffer surface state size
311 - isl: Fix isl_tiling_is_any_y()
H A D13.0.2.rst120 - isl: Fix height calculation in isl_msaa_interleaved_scale_px_to_sa
H A D17.1.1.rst128 - intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
H A D18.1.3.rst93 - meson: fix i965/anv/isl genX static lib names
H A D18.1.8.rst143 - intel/isl: Avoid tiling some 16K-wide render targets
H A D19.0.1.rst129 - isl: fix automake build when sse41 is not supported
H A D19.1.2.rst129 - isl: Don't align phys_level0_sa by block dimension
/xsrc/external/mit/MesaLib/dist/docs/
H A Dindex.rst115 isl/index

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