Searched refs:layer_ctrl (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc_1_1.c265 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
266 enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
269 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
270 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
453 layer_ctrl.max_num_temporal_layers - 1, 3);
463 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
466 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
467 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
636 enc->enc_pic.layer_ctrl.
648 for (i = 0; i < (enc->enc_pic.layer_ctrl
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H A Dradeon_vcn_enc_1_2.c256 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
257 enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
260 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
261 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
506 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
567 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
577 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
580 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
581 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
744 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl
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H A Dradeon_uvd_enc.h407 ruvd_enc_layer_control_t layer_ctrl; member in struct:radeon_uvd_enc_pic
H A Dradeon_vcn_enc.h427 rvcn_enc_layer_control_t layer_ctrl; member in struct:radeon_enc_pic
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc_1_1.c243 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
244 enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
247 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
248 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
404 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
414 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
417 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
418 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
562 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
573 for (i = 0; i < (enc->enc_pic.layer_ctrl
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H A Dradeon_vcn_enc_1_2.c139 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers;
140 enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers;
143 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
144 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
317 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
379 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
389 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
392 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
393 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
468 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl
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H A Dradeon_vcn_enc_2_0.c259 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
274 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
277 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
278 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
H A Dradeon_uvd_enc.h371 ruvd_enc_layer_control_t layer_ctrl; member in struct:radeon_uvd_enc_pic
H A Dradeon_vcn_enc.h458 rvcn_enc_layer_control_t layer_ctrl; member in struct:radeon_enc_pic

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