Searched refs:lri (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_state.c84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
85 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
86 lri.DataDWord = cache_mode_0;
122 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
123 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
124 lri.DataDWord = cache_mode_1;
185 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
186 lri.RegisterOffset = GENX(SAMPLER_MODE_num);
187 lri.DataDWord = sampler_mode;
198 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
[all...]
H A Dgen8_cmd_buffer.c134 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
135 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
136 lri.DataDWord = cache_mode;
147 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
148 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
149 lri.DataDWord = cache_mode;
H A DgenX_cmd_buffer.c45 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
46 lri.RegisterOffset = reg;
47 lri.DataDWord = imm;
3352 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
3353 lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
3354 lri.DataDWord = 0;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_genx_macros.h130 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
131 lri.RegisterOffset = __genxml_reg_num(reg); \
132 lri.DataDWord = _dw[i]; \
H A Dcrocus_state.c520 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
521 lri.RegisterOffset = reg;
522 lri.DataDWord = val;
7971 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
7972 lri.RegisterOffset = _3DPRIM_BASE_VERTEX;
7973 lri.DataDWord = 0;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_genx_macros.h125 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
126 lri.RegisterOffset = __genxml_reg_num(reg); \
127 lri.DataDWord = _dw[i]; \
H A Diris_state.c476 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
477 lri.RegisterOffset = reg;
478 lri.DataDWord = val;
6820 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
6821 lri.RegisterOffset = _3DPRIM_BASE_VERTEX;
6822 lri.DataDWord = 0;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c130 static bool live_reg_is_upper_half(uint32_t lri) argument
132 return (lri >=16 && lri < 32) ||
133 (lri >=32 + 16 && lri < 32 + 32);
387 u32 lri = waddr_to_live_reg_index(waddr, is_b); local in function:check_reg_write
389 if (lri != -1) {
397 validation_state->live_immediates[lri] =
400 validation_state->live_immediates[lri] = ~0;
403 if (live_reg_is_upper_half(lri))
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c130 static bool live_reg_is_upper_half(uint32_t lri) argument
132 return (lri >=16 && lri < 32) ||
133 (lri >=32 + 16 && lri < 32 + 32);
387 u32 lri = waddr_to_live_reg_index(waddr, is_b); local in function:check_reg_write
389 if (lri != -1) {
397 validation_state->live_immediates[lri] =
400 validation_state->live_immediates[lri] = ~0;
403 if (live_reg_is_upper_half(lri))
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_state.c280 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
281 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
282 lri.DataDWord = aux_base_addr & 0xffffffff;
284 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
285 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
286 lri.DataDWord = aux_base_addr >> 32;
H A Dgfx8_cmd_buffer.c167 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
168 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
169 lri.DataDWord = cache_mode;
180 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
181 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
182 lri.DataDWord = cache_mode;
H A DgenX_cmd_buffer.c2395 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2396 lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num);
2397 lri.DataDWord = 1;
4658 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
4659 lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4;
4660 lri.DataDWord = 0;
H A Danv_private.h1749 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
1750 lri.RegisterOffset = __anv_reg_num(reg); \
1751 lri.DataDWord = _dw[i]; \
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dmi_builder.h388 mi_builder_pack(b, GENX(MI_LOAD_REGISTER_IMM), dw, lri) {
389 lri.DWordLength = GENX(MI_LOAD_REGISTER_IMM_length) + 2 -
392 lri.AddCSMMIOStartOffset = reg.cs;
490 mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) {
492 lri.RegisterOffset = reg.num;
494 lri.AddCSMMIOStartOffset = reg.cs;
496 lri.DataDWord = src.imm;
/xsrc/external/mit/MesaLib.old/dist/src/intel/common/
H A Dgen_mi_builder.h400 gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) {
401 lri.RegisterOffset = dst.reg;
402 lri.DataDWord = src.imm;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_state.c495 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
496 lri.RegisterOffset = reg;
497 lri.DataDWord = val;
5366 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
5367 lri.RegisterOffset = _3DPRIM_BASE_VERTEX;
5368 lri.DataDWord = 0;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c89 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
90 lri.RegisterOffset = reg;
91 lri.DataDWord = imm;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c93 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
94 lri.RegisterOffset = reg;
95 lri.DataDWord = imm;

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