Searched refs:meta_slice_size (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_copy_vrs_htile.c287 dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size,
H A Dradv_meta_clear.c1476 offset += image->planes[0].surface.meta_slice_size * range->baseArrayLayer +
1656 uint64_t size = image->planes[0].surface.meta_slice_size * layer_count;
1658 image->planes[0].surface.meta_slice_size * range->baseArrayLayer;
H A Dradv_cmd_buffer.c5771 uint64_t htile_size = ds_image->planes[0].surface.meta_slice_size;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h369 uint32_t meta_slice_size; member in struct:radeon_surf
H A Dac_surface.c718 surf->meta_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
744 surf->meta_slice_size != dcc_level->dcc_slice_fast_clear_size) {
772 surf->meta_slice_size = AddrHtileOut->sliceSize;
1165 surf->meta_slice_size = 0;
1749 surf->meta_slice_size = hout.sliceSize;
1844 surf->meta_slice_size = dout.dccRamSliceSize;
2229 surf->meta_slice_size = 0;
3016 nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size,
3064 return nir_iadd(b, nir_iadd(b, nir_imul(b, meta_slice_size, z),
3013 gfx10_nir_meta_addr_from_coord(nir_builder * b,const struct radeon_info * info,struct gfx9_meta_equation * equation,int blkSizeBias,unsigned blkStart,nir_ssa_def * meta_pitch,nir_ssa_def * meta_slice_size,nir_ssa_def * x,nir_ssa_def * y,nir_ssa_def * z,nir_ssa_def * pipe_xor,nir_ssa_def ** bit_position) argument
H A Dac_surface_meta_address_test.c126 unsigned meta_pitch, unsigned meta_slice_size,
167 return (meta_slice_size * z) +
120 gfx10_meta_addr_from_coord(const struct radeon_info * info,const uint16_t * equation,unsigned meta_block_width,unsigned meta_block_height,unsigned blkSizeLog2,unsigned meta_pitch,unsigned meta_slice_size,unsigned x,unsigned y,unsigned z,unsigned pipe_xor,unsigned * bit_position) argument

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