| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_meta_decompress.c | 38 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
91 &device->meta_state.alloc,
108 mtx_lock(&device->meta_state.mtx);
110 mtx_unlock(&device->meta_state.mtx);
204 radv_pipeline_cache_to_handle(&device->meta_state.cache),
211 &device->meta_state.alloc,
217 radv_pipeline_cache_to_handle(&device->meta_state.cache),
225 &device->meta_state.alloc,
236 mtx_unlock(&device->meta_state.mtx);
243 struct radv_meta_state *state = &device->meta_state;
330 struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; local in function:radv_process_depth_image_inplace
[all...] |
| H A D | radv_meta_blit2d.c | 128 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
143 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
151 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
156 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
214 cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
226 cmd_buffer->device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type];
238 cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type];
283 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
294 if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] == VK_NULL_HANDLE) {
305 .renderPass = device->meta_state
[all...] |
| H A D | radv_meta_bufimage.c | 169 &device->meta_state.alloc,
170 &device->meta_state.itob.img_ds_layout);
178 .pSetLayouts = &device->meta_state.itob.img_ds_layout,
185 &device->meta_state.alloc,
186 &device->meta_state.itob.img_p_layout);
204 .layout = device->meta_state.itob.img_p_layout,
208 radv_pipeline_cache_to_handle(&device->meta_state.cache),
210 &device->meta_state.itob.pipeline);
227 .layout = device->meta_state.itob.img_p_layout,
231 radv_pipeline_cache_to_handle(&device->meta_state
[all...] |
| H A D | radv_meta_fast_clear.c | 137 &device->meta_state.alloc,
138 &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout);
146 .pSetLayouts = &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout,
153 &device->meta_state.alloc,
154 &device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout);
172 .layout = device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout,
176 radv_pipeline_cache_to_handle(&device->meta_state.cache),
178 &device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
192 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
228 &device->meta_state
[all...] |
| H A D | radv_meta_buffer.c | 149 &device->meta_state.alloc,
150 &device->meta_state.buffer.fill_ds_layout);
178 &device->meta_state.alloc,
179 &device->meta_state.buffer.copy_ds_layout);
187 .pSetLayouts = &device->meta_state.buffer.fill_ds_layout,
194 &device->meta_state.alloc,
195 &device->meta_state.buffer.fill_p_layout);
202 .pSetLayouts = &device->meta_state.buffer.copy_ds_layout,
208 &device->meta_state.alloc,
209 &device->meta_state
[all...] |
| H A D | radv_meta_blit.c | 330 device->meta_state.blit.pipeline_layout,
356 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
367 pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
370 pipeline = &device->meta_state.blit.pipeline_2d_src[fs_key];
373 pipeline = &device->meta_state.blit.pipeline_3d_src[fs_key];
385 .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
396 pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
399 pipeline = &device->meta_state.blit.depth_only_2d_pipeline;
402 pipeline = &device->meta_state.blit.depth_only_3d_pipeline;
414 .renderPass = device->meta_state
[all...] |
| H A D | radv_meta_resolve_fs.c | 128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
164 mtx_lock(&device->meta_state.mtx);
167 VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
169 mtx_unlock(&device->meta_state.mtx);
187 VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][0];
239 }, &device->meta_state
[all...] |
| H A D | radv_meta_resolve.c | 58 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
135 if (!device->meta_state.resolve.p_layout) {
138 &device->meta_state.alloc,
139 &device->meta_state.resolve.p_layout);
145 radv_pipeline_cache_to_handle(&device->meta_state.cache),
219 .layout = device->meta_state.resolve.p_layout,
227 &device->meta_state.alloc, pipeline);
241 struct radv_meta_state *state = &device->meta_state;
261 struct radv_meta_state *state = &device->meta_state;
307 device->meta_state
[all...] |
| H A D | radv_meta_resolve_cs.c | 175 &device->meta_state.alloc,
176 &device->meta_state.resolve_compute.ds_layout);
184 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
191 &device->meta_state.alloc,
192 &device->meta_state.resolve_compute.p_layout);
210 mtx_lock(&device->meta_state.mtx);
212 mtx_unlock(&device->meta_state.mtx);
232 .layout = device->meta_state.resolve_compute.p_layout,
236 radv_pipeline_cache_to_handle(&device->meta_state.cache),
243 mtx_unlock(&device->meta_state
[all...] |
| H A D | radv_meta.c | 280 ret = radv_pipeline_cache_load(&device->meta_state.cache, data, st.st_size);
294 if (!device->meta_state.cache.modified)
298 radv_pipeline_cache_to_handle(&device->meta_state.cache),
315 radv_pipeline_cache_to_handle(&device->meta_state.cache),
333 memset(&device->meta_state, 0, sizeof(device->meta_state));
335 device->meta_state.alloc = (VkAllocationCallbacks) {
342 device->meta_state.cache.alloc = device->meta_state.alloc;
343 radv_pipeline_cache_init(&device->meta_state
[all...] |
| H A D | radv_meta_clear.c | 115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
203 mtx_lock(&device->meta_state.mtx);
205 mtx_unlock (&device->meta_state.mtx);
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
255 mtx_lock(&device->meta_state.mtx);
257 mtx_unlock(&device->meta_state.mtx);
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
302 mtx_unlock(&device->meta_state
661 pick_depthstencil_pipeline(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_state * meta_state,const struct radv_image_view * iview,int samples_log2,VkImageAspectFlags aspects,VkImageLayout layout,const VkClearRect * clear_rect,VkClearDepthStencilValue clear_value) argument
721 struct radv_meta_state *meta_state = &device->meta_state; local in function:emit_depthstencil_clear
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_meta_blit2d.c | 118 device->meta_state.blit2d[log2_samples].p_layouts[src_type], 0, /* set */
129 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
136 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
141 device->meta_state.blit2d[log2_samples].p_layouts[src_type], 0, /* set */
190 cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
201 cmd_buffer->device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type];
212 cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type];
257 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
267 if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] ==
281 .renderPass = device->meta_state
[all...] |
| H A D | radv_meta_dcc_retile.c | 87 struct radv_meta_state *state = &device->meta_state;
134 &device->meta_state.alloc,
135 &device->meta_state.dcc_retile.ds_layout);
142 .pSetLayouts = &device->meta_state.dcc_retile.ds_layout,
149 &device->meta_state.alloc, &device->meta_state.dcc_retile.p_layout);
167 .layout = device->meta_state.dcc_retile.p_layout,
171 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
172 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
201 if (!cmd_buffer->device->meta_state
[all...] |
| H A D | radv_meta_bufimage.c | 128 &device->meta_state.alloc,
129 &device->meta_state.itob.img_ds_layout);
136 .pSetLayouts = &device->meta_state.itob.img_ds_layout,
143 &device->meta_state.alloc, &device->meta_state.itob.img_p_layout);
161 .layout = device->meta_state.itob.img_p_layout,
165 radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
166 &vk_pipeline_info, NULL, &device->meta_state.itob.pipeline);
183 .layout = device->meta_state.itob.img_p_layout,
187 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state
[all...] |
| H A D | radv_meta_fast_clear.c | 104 radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
105 &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout);
112 .pSetLayouts = &device->meta_state.fast_clear_flush.dcc_decompress_compute_ds_layout,
118 radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
119 &device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout);
137 .layout = device->meta_state.fast_clear_flush.dcc_decompress_compute_p_layout,
141 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
143 &device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
157 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
218 alloc, &device->meta_state
[all...] |
| H A D | radv_meta_buffer.c | 74 &device->meta_state.alloc,
75 &device->meta_state.buffer.fill_ds_layout);
97 &device->meta_state.alloc,
98 &device->meta_state.buffer.copy_ds_layout);
105 .pSetLayouts = &device->meta_state.buffer.fill_ds_layout,
111 &device->meta_state.alloc,
112 &device->meta_state.buffer.fill_p_layout);
119 .pSetLayouts = &device->meta_state.buffer.copy_ds_layout,
124 &device->meta_state.alloc,
125 &device->meta_state
[all...] |
| H A D | radv_meta_blit.c | 264 device->meta_state.blit.pipeline_layout, VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
292 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
305 pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
308 pipeline = &device->meta_state.blit.pipeline_2d_src[fs_key];
311 pipeline = &device->meta_state.blit.pipeline_3d_src[fs_key];
324 .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
337 pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
340 pipeline = &device->meta_state.blit.depth_only_2d_pipeline;
343 pipeline = &device->meta_state.blit.depth_only_3d_pipeline;
356 .renderPass = device->meta_state
[all...] |
| H A D | radv_meta_resolve_fs.c | 100 &device->meta_state.alloc,
101 &device->meta_state.resolve_fragment.ds_layout);
108 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
114 &device->meta_state.alloc,
115 &device->meta_state.resolve_fragment.p_layout);
132 mtx_lock(&device->meta_state.mtx);
135 VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
137 mtx_unlock(&device->meta_state.mtx);
152 VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][0];
227 &device->meta_state
[all...] |
| H A D | radv_query.c | 623 mtx_lock(&device->meta_state.mtx);
624 if (device->meta_state.query.pipeline_statistics_query_pipeline) {
625 mtx_unlock(&device->meta_state.mtx);
651 &device->meta_state.alloc,
652 &device->meta_state.query.ds_layout);
659 .pSetLayouts = &device->meta_state.query.ds_layout,
666 &device->meta_state.alloc, &device->meta_state.query.p_layout);
682 .layout = device->meta_state.query.p_layout,
686 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state
[all...] |
| H A D | radv_meta_clear.c | 89 device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
180 mtx_lock(&device->meta_state.mtx);
182 mtx_unlock(&device->meta_state.mtx);
243 &device->meta_state.alloc, pass);
244 mtx_unlock(&device->meta_state.mtx);
256 mtx_lock(&device->meta_state.mtx);
258 mtx_unlock(&device->meta_state.mtx);
296 &vi_state, &ds_state, &cb_state, device->meta_state.clear_color_p_layout,
297 &extra, &device->meta_state.alloc, pipeline);
299 mtx_unlock(&device->meta_state
676 pick_depthstencil_pipeline(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_state * meta_state,const struct radv_image_view * iview,int samples_log2,VkImageAspectFlags aspects,VkImageLayout layout,bool in_render_loop,const VkClearRect * clear_rect,VkClearDepthStencilValue clear_value) argument
735 struct radv_meta_state *meta_state = &device->meta_state; local in function:emit_depthstencil_clear
[all...] |
| H A D | radv_meta_resolve_cs.c | 256 &device->meta_state.alloc,
257 &device->meta_state.resolve_compute.ds_layout);
264 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
270 &device->meta_state.alloc,
271 &device->meta_state.resolve_compute.p_layout);
285 mtx_lock(&device->meta_state.mtx);
287 mtx_unlock(&device->meta_state.mtx);
307 .layout = device->meta_state.resolve_compute.p_layout,
311 radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
317 mtx_unlock(&device->meta_state
[all...] |
| H A D | radv_meta_decompress.c | 105 radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
106 &device->meta_state.expand_depth_stencil_compute_ds_layout);
113 .pSetLayouts = &device->meta_state.expand_depth_stencil_compute_ds_layout,
119 radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
120 &device->meta_state.expand_depth_stencil_compute_p_layout);
138 .layout = device->meta_state.expand_depth_stencil_compute_p_layout,
142 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
144 &device->meta_state.expand_depth_stencil_compute_pipeline);
158 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
233 &device->meta_state
[all...] |
| H A D | radv_meta_resolve.c | 54 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
152 if (!device->meta_state.resolve.p_layout) {
155 &device->meta_state.alloc, &device->meta_state.resolve.p_layout);
161 device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache),
242 .layout = device->meta_state.resolve.p_layout,
250 &device->meta_state.alloc, pipeline);
264 struct radv_meta_state *state = &device->meta_state;
282 struct radv_meta_state *state = &device->meta_state;
330 device->meta_state
[all...] |
| H A D | radv_meta.h | 261 struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; local in function:radv_is_fmask_decompress_pipeline
265 meta_state->fast_clear_flush.fmask_decompress_pipeline;
274 struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; local in function:radv_is_dcc_decompress_pipeline
277 return radv_pipeline_to_handle(pipeline) == meta_state->fast_clear_flush.dcc_decompress_pipeline;
|
| H A D | radv_meta_fmask_expand.c | 105 VkPipeline pipeline = device->meta_state.fmask_expand.pipeline[samples_log2];
132 cmd_buffer->device->meta_state.fmask_expand.p_layout, 0, /* set */
173 struct radv_meta_state *state = &device->meta_state;
189 struct radv_meta_state *state = &device->meta_state;
220 struct radv_meta_state *state = &device->meta_state;
|