Searched refs:mux_a (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_pack.c471 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
488 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
604 uint32_t mux_a, uint32_t mux_b)
619 if (!(op_desc->mux_a_mask & (1 << mux_a)))
746 uint32_t mux_a = QPU_GET_FIELD(packed_inst, V3D_QPU_ADD_A); local in function:v3d_qpu_add_unpack
761 map_op, mux_a, mux_b);
771 if (((op >> 2) & 3) * 8 + mux_a > (op & 3) * 8 + mux_b) {
871 instr->alu.add.a = mux_a;
901 uint32_t mux_a = QPU_GET_FIELD(packed_inst, V3D_QPU_MUL_A); local in function:v3d_qpu_mul_unpack
908 op, mux_a, mux_
601 lookup_opcode_from_packed(const struct v3d_device_info * devinfo,const struct opcode_desc * opcodes,size_t num_opcodes,uint32_t opcode,uint32_t mux_a,uint32_t mux_b) argument
994 uint32_t mux_a = instr->alu.add.a; local in function:v3d_qpu_add_pack
1206 uint32_t mux_a = instr->alu.mul.a; local in function:v3d_qpu_mul_pack
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_pack.c463 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
480 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
577 uint32_t opcode, uint32_t mux_a, uint32_t mux_b)
589 if (!(op_desc->mux_a_mask & (1 << mux_a)))
716 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A); local in function:v3d_qpu_add_unpack
731 map_op, mux_a, mux_b);
740 if (((op >> 2) & 3) * 8 + mux_a > (op & 3) * 8 + mux_b) {
840 instr->alu.add.a = mux_a;
870 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A); local in function:v3d_qpu_mul_unpack
876 op, mux_a, mux_
576 lookup_opcode(const struct opcode_desc * opcodes,size_t num_opcodes,uint32_t opcode,uint32_t mux_a,uint32_t mux_b) argument
942 uint32_t mux_a = instr->alu.add.a; local in function:v3d_qpu_add_pack
1158 uint32_t mux_a = instr->alu.mul.a; local in function:v3d_qpu_mul_pack
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c278 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A); local in function:vc4_qpu_validate
285 if (mux_a > QPU_MUX_R3 || mux_b > QPU_MUX_R3) {
308 if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
H A Dvc4_qpu_schedule.c491 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A); local in function:reads_too_soon_after_write
494 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
496 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_validate.c280 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A); local in function:vc4_qpu_validate
287 if (mux_a > QPU_MUX_R3 || mux_b > QPU_MUX_R3) {
310 if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
H A Dvc4_qpu_schedule.c491 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A); local in function:reads_too_soon_after_write
494 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
496 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dqpu_schedule.c1917 enum v3d_qpu_mux mux_a, mux_b; local in function:alu_reads_register
1921 mux_a = inst->alu.add.a;
1925 mux_a = inst->alu.mul.a;
1931 if (i == 0 && mux_a == index)
1936 if (i == 0 && mux_a == V3D_QPU_MUX_A &&
1940 if (i == 0 && mux_a == V3D_QPU_MUX_B &&

Completed in 12 milliseconds