Searched refs:n_passes (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_query.c72 uint32_t n_passes = 0; local in function:genX
140 n_passes = intel_perf_get_n_passes(pdevice->perf,
147 n_passes);
156 uint64s_per_slot *= n_passes;
179 pool->pass_size = pool->stride / n_passes;
188 pool->n_passes = n_passes;
208 for (uint32_t p = 0; p < pool->n_passes; p++) {
401 for (uint32_t p = 0; p < pool->n_passes; p++) {
553 for (uint32_t p = 0; p < pool->n_passes;
[all...]
H A Danv_batch_chain.c2005 assert(submit->perf_query_pass < query_pool->n_passes);
H A Danv_private.h4643 uint32_t n_passes; member in struct:anv_query_pool
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_query.c1471 uint32_t gid = 0, cid = 0, n_passes; local in function:tu_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR
1488 n_passes = DIV_ROUND_UP(counters_requested[i], group[i].num_counters);
1489 *pNumPasses = MAX2(*pNumPasses, n_passes);
/xsrc/external/mit/MesaLib/dist/src/intel/perf/
H A Dintel_perf.c920 ASSERTED uint32_t n_passes = util_bitcount64(queries_mask); local in function:intel_perf_get_counters_passes
933 assert(counter_pass[i].pass < n_passes);

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