Searched refs:offset_src (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_opt_uniform_atomics.c43 parse_atomic_op(nir_intrinsic_op op, unsigned *offset_src, unsigned *data_src) argument
48 *offset_src = 1; \
54 *offset_src = 0; \
62 *offset_src = 1; \
197 unsigned offset_src, data_src; local in function:optimize_atomic
198 nir_op op = parse_atomic_op(intrin->intrinsic, &offset_src, &data_src);
282 unsigned offset_src, data_src; local in function:opt_uniform_atomics
283 if (parse_atomic_op(intrin->intrinsic, &offset_src, &data_src) == nir_num_opcodes)
286 if (nir_src_is_divergent(intrin->src[offset_src]))
H A Dnir_lower_wrmasks.c78 offset_src(nir_intrinsic_op intrinsic) function in typeref:typename:int
105 unsigned offset_idx = offset_src(intr->intrinsic);
209 assert(offset_src(intr->intrinsic) >= 0);
H A Dnir_gather_ssa_types.c209 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:nir_gather_ssa_types
210 if (offset_src) {
211 assert(offset_src->is_ssa);
212 set_type(offset_src->ssa->index, nir_type_int,
H A Dnir_lower_ssbo.c115 nir_src *offset_src = nir_get_io_offset_src(intr); local in function:lower_ssbo_instr
116 nir_ssa_def *offset = nir_ssa_for_src(b, *offset_src, 1);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_nir_lower_mem_access_bit_sizes.c99 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:lower_mem_load_bit_size
100 if (bit_size < 32 && !needs_scalar && nir_src_is_const(*offset_src)) {
104 const int load_offset = nir_src_as_uint(*offset_src) % 4;
182 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:lower_mem_store_bit_size
183 const bool offset_is_const = nir_src_is_const(*offset_src);
185 offset_is_const ? nir_src_as_uint(*offset_src) : 0;
H A Dbrw_fs.h319 unsigned base_offset, const nir_src &offset_src,
H A Dbrw_vec4_nir.cpp268 nir_src *offset_src = nir_get_io_offset_src(instr); local in function:brw::vec4_visitor::get_indirect_offset
270 if (nir_src_is_const(*offset_src)) {
275 assert(nir_src_as_uint(*offset_src) == 0);
279 return get_nir_src(*offset_src, BRW_REGISTER_TYPE_UD, 1);
H A Dbrw_fs_nir.cpp2501 const nir_src &offset_src,
2511 nir_src_is_const(offset_src) && nir_src_is_const(vertex_src) &&
2512 4 * (base_offset + nir_src_as_uint(offset_src)) < push_reg_count) {
2513 int imm_offset = (base_offset + nir_src_as_uint(offset_src)) * 4 +
2604 fs_reg indirect_offset = get_nir_src(offset_src);
2606 if (nir_src_is_const(offset_src)) {
2623 inst->offset = base_offset + nir_src_as_uint(offset_src);
2654 nir_src *offset_src = nir_get_io_offset_src(instr); local in function:fs_visitor::get_indirect_offset
2656 if (nir_src_is_const(*offset_src)) {
2661 assert(nir_src_as_uint(*offset_src)
2498 emit_gs_input_load(const fs_reg & dst,const nir_src & vertex_src,unsigned base_offset,const nir_src & offset_src,unsigned num_components,unsigned first_component) argument
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/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dv3d_nir_lower_robust_buffer_access.c31 uint32_t offset_src,
49 nir_umin(b, instr->src[offset_src].ssa, aligned_buffer_size);
50 nir_instr_rewrite_src(&instr->instr, &instr->src[offset_src],
28 rewrite_offset(nir_builder * b,nir_intrinsic_instr * instr,uint32_t buffer_idx,uint32_t offset_src,nir_intrinsic_op buffer_size_op) argument
H A Dnir_to_vir.c433 int offset_src,
441 ntq_get_src(c, instr->src[offset_src], 0);
463 struct qreg data = ntq_get_src(c, instr->src[offset_src], 0);
518 int offset_src; local in function:ntq_emit_tmu_general
520 offset_src = 0;
526 offset_src = 0 + has_index;
528 offset_src = 1 + has_index;
530 offset_src = 0 + has_index;
533 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
536 const_offset = nir_src_as_uint(instr->src[offset_src]);
428 emit_tmu_general_address_write(struct v3d_compile * c,enum emit_mode mode,nir_intrinsic_instr * instr,uint32_t config,bool dynamic_src,int offset_src,struct qreg base_offset,uint32_t const_offset,uint32_t * tmu_writes) argument
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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_nir_lower_mem_access_bit_sizes.c90 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:lower_mem_load_bit_size
91 if (bit_size < 32 && nir_src_is_const(*offset_src)) {
95 const int load_offset = nir_src_as_uint(*offset_src) % 4;
177 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:lower_mem_store_bit_size
178 const bool offset_is_const = nir_src_is_const(*offset_src);
180 offset_is_const ? nir_src_as_uint(*offset_src) : 0;
H A Dbrw_fs_nir.cpp2320 const nir_src &offset_src,
2331 nir_src_is_const(offset_src) && nir_src_is_const(vertex_src) &&
2332 4 * (base_offset + nir_src_as_uint(offset_src)) < push_reg_count) {
2333 int imm_offset = (base_offset + nir_src_as_uint(offset_src)) * 4 +
2426 fs_reg indirect_offset = get_nir_src(offset_src);
2441 if (nir_src_is_const(offset_src)) {
2459 inst->offset = base_offset + nir_src_as_uint(offset_src);
2497 if(nir_src_is_const(offset_src)) {
2511 nir_src *offset_src = nir_get_io_offset_src(instr); local in function:fs_visitor::get_indirect_offset
2513 if (nir_src_is_const(*offset_src)) {
2317 emit_gs_input_load(const fs_reg & dst,const nir_src & vertex_src,unsigned base_offset,const nir_src & offset_src,unsigned num_components,unsigned first_component) argument
3554 fs_reg offset_src = retype(get_nir_src(instr->src[0]), local in function:fs_visitor::nir_emit_fs_intrinsic
[all...]
H A Dbrw_fs.h279 unsigned base_offset, const nir_src &offset_src,
H A Dbrw_vec4_nir.cpp267 nir_src *offset_src = nir_get_io_offset_src(instr); local in function:brw::vec4_visitor::get_indirect_offset
269 if (nir_src_is_const(*offset_src)) {
274 assert(nir_src_as_uint(*offset_src) == 0);
278 return get_nir_src(*offset_src, BRW_REGISTER_TYPE_UD, 1);
/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir_gather_ssa_types.c188 nir_src *offset_src = nir_get_io_offset_src(intrin); local in function:nir_gather_ssa_types
189 if (offset_src) {
190 assert(offset_src->is_ssa);
191 set_type(offset_src->ssa->index, nir_type_int,
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dnir_to_vir.c194 int offset_src; local in function:ntq_emit_tmu_general
197 offset_src = 0;
202 offset_src = 0 + has_index;
204 offset_src = 1 + has_index;
212 offset_src = 0 + has_index;
226 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
229 const_offset = nir_src_as_uint(instr->src[offset_src]);
307 ntq_get_src(c, instr->src[offset_src], 0));
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi.c2695 int offset_src = -1; local in function:nir_to_tgsi_lower_64bit_intrinsic
2701 offset_src = 1;
2704 offset_src = 1;
2708 offset_src = 2;
2713 if (offset_src != -1) {
2716 nir_iadd_imm(b, second->src[offset_src].ssa, offset_amount);
2717 nir_instr_rewrite_src(&second->instr, &second->src[offset_src],
/xsrc/external/mit/MesaLib/dist/src/asahi/compiler/
H A Dagx_compile.c139 nir_src *offset_src = nir_get_io_offset_src(instr); local in function:agx_emit_load_attr
140 assert(nir_src_is_const(*offset_src) && "no attribute indirects");
142 nir_src_as_uint(*offset_src);
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/tests/
H A Dload_store_vectorizer_tests.cpp240 int offset_src = res ? 1 : 0; local in function:__anon343ea75b0110::nir_load_store_vectorize_test::create_indirect_load
242 if (nir_src_is_const(load->src[offset_src])) {
243 nir_intrinsic_set_range_base(load, nir_src_as_uint(load->src[offset_src]));
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_nir_to_llvm.c4130 LLVMValueRef offset_src = ac_extract_components(&ctx->ac, src, start, count); local in function:visit_intrinsic
4131 LLVMBuildStore(ctx->ac.builder, offset_src, offset_ptr);
4551 unsigned offset_src = 0; local in function:visit_tex
4576 offset_src = i;
4799 int num_offsets = instr->src[offset_src].src.ssa->num_components;
/xsrc/external/mit/MesaLib/dist/src/microsoft/compiler/
H A Dnir_to_dxil.c2654 const struct dxil_value *offset_src = get_src(ctx, &intr->src[1], 0, nir_type_uint); local in function:emit_load_ubo
2656 if (!offset_src || !c4)
2659 offset = dxil_emit_binop(&ctx->mod, DXIL_BINOP_ASHR, offset_src, c4, 0);
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_nir_to_llvm.c3669 unsigned offset_src = 0; local in function:visit_tex
3689 offset_src = i;
3885 int num_offsets = instr->src[offset_src].src.ssa->num_components;
3890 LLVMConstInt(ctx->ac.i32, nir_src_comp_as_uint(instr->src[offset_src].src, i), false), "");
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c8093 struct tgsi_full_src_register offset_src, sampler, ref; local in function:emit_tg4
8172 offset_src = make_src_reg(inst->TexOffsets[0].File,
8174 offset_src = swizzle_src(&offset_src, inst->TexOffsets[0].SwizzleX,
8178 emit_src_register(emit, &offset_src);

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