Searched refs:operand0 (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
390 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
393 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
404 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
405 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
409 i915_get_hardware_channel_val(REG_Y(operand0), \
412 i915_get_hardware_channel_val(REG_Z(operand0), \
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
390 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
393 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
404 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
405 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
406 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
409 i915_get_hardware_channel_val(REG_Y(operand0), \
412 i915_get_hardware_channel_val(REG_Z(operand0), \
[all...]
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h266 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
267 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
271 struct i915_fs_operand operand0,
288 op.ui[0] |= REG_TYPE(operand0.reg) << A0_SRC0_TYPE_SHIFT;
289 op.ui[0] |= REG_NR(operand0.reg) << A0_SRC0_NR_SHIFT;
291 op.ui[1] |= i915_get_hardware_channel_val(operand0.x) <<
293 if (operand0.x < 0)
296 op.ui[1] |= i915_get_hardware_channel_val(operand0.y) <<
298 if (operand0.y < 0)
301 op.ui[1] |= i915_get_hardware_channel_val(operand0
270 _i915_fs_arith(int cmd,int dest_reg,struct i915_fs_operand operand0,struct i915_fs_operand operand1,struct i915_fs_operand operand2) argument
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1236 #define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
1237 _gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
1239 #define gen3_fs_arith(op, dest_reg, operand0, operand1, operand2) \
1240 _gen3_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
1242 #define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
1251 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
1252 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
1253 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1256 gen3_get_hardware_channel_val(REG_Y(operand0), \
1259 gen3_get_hardware_channel_val(REG_Z(operand0), \
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1236 #define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
1237 _gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
1239 #define gen3_fs_arith(op, dest_reg, operand0, operand1, operand2) \
1240 _gen3_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
1242 #define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
1251 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
1252 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
1253 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \
1256 gen3_get_hardware_channel_val(REG_Y(operand0), \
1259 gen3_get_hardware_channel_val(REG_Z(operand0), \
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c762 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
767 VGPU10OperandToken0 operand0,
777 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 ||
778 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
781 assert(operand0.selectionMode == 0);
786 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
826 operand0.indexDimension = indexDim;
827 operand0.index0Representation = index0Rep;
828 operand0.index1Representation = index1Rep;
830 return operand0;
766 setup_operand0_indexing(struct svga_shader_emitter_v10 * emit,VGPU10OperandToken0 operand0,enum tgsi_file_type file,boolean indirect,boolean index2D,unsigned tempArrayID) argument
844 VGPU10OperandToken0 operand0; local in function:emit_indirect_register
884 VGPU10OperandToken0 operand0; local in function:emit_dst_register
1019 VGPU10OperandToken0 operand0; local in function:emit_src_register
1177 VGPU10OperandToken0 operand0; local in function:emit_resource_register
1205 VGPU10OperandToken0 operand0; local in function:emit_sampler_register
1226 VGPU10OperandToken0 operand0; local in function:emit_face_register
1254 VGPU10OperandToken0 operand0; local in function:emit_rasterizer_register
2118 emit_decl_instruction(struct svga_shader_emitter_v10 * emit,VGPU10OpcodeToken0 opcode0,VGPU10OperandToken0 operand0,VGPU10NameToken name_token,unsigned index,unsigned size) argument
2182 VGPU10OperandToken0 operand0; local in function:emit_input_declaration
2249 VGPU10OperandToken0 operand0; local in function:emit_output_declaration
2287 VGPU10OperandToken0 operand0; local in function:emit_fragdepth_output_declaration
2311 VGPU10OperandToken0 operand0; local in function:emit_samplemask_output_declaration
3034 VGPU10OperandToken0 operand0; local in function:emit_constant_declaration
3139 VGPU10OperandToken0 operand0; local in function:emit_sampler_declarations
3255 VGPU10OperandToken0 operand0; local in function:emit_resource_declarations
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c1085 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
1094 VGPU10OperandToken0 operand0,
1105 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 ||
1106 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID ||
1107 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID ||
1108 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID ||
1109 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP ||
1110 operand0.operandType == VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID) {
1113 assert(operand0.selectionMode == 0);
1115 else if (operand0
1093 setup_operand0_indexing(struct svga_shader_emitter_v10 * emit,VGPU10OperandToken0 operand0,enum tgsi_file_type file,boolean indirect,boolean index2D,bool indirect2D) argument
1161 VGPU10OperandToken0 operand0; local in function:emit_indirect_register
1201 VGPU10OperandToken0 operand0; local in function:emit_dst_register
1490 VGPU10OperandToken0 operand0; local in function:emit_src_register
1850 VGPU10OperandToken0 operand0; local in function:emit_resource_register
1878 VGPU10OperandToken0 operand0; local in function:emit_sampler_register
1899 VGPU10OperandToken0 operand0; local in function:emit_face_register
1927 VGPU10OperandToken0 operand0; local in function:emit_rasterizer_register
1953 VGPU10OperandToken0 operand0; local in function:emit_stream_register
3424 VGPU10OperandToken0 operand0; local in function:emit_index_range_declaration
3476 emit_decl_instruction(struct svga_shader_emitter_v10 * emit,VGPU10OpcodeToken0 opcode0,VGPU10OperandToken0 operand0,VGPU10NameToken name_token,unsigned index,unsigned size) argument
3549 VGPU10OperandToken0 operand0; local in function:emit_input_declaration
3703 VGPU10OperandToken0 operand0; local in function:emit_output_declaration
3795 VGPU10OperandToken0 operand0; local in function:emit_fragdepth_output_declaration
3819 VGPU10OperandToken0 operand0; local in function:emit_samplemask_output_declaration
4123 VGPU10OperandToken0 operand0; local in function:emit_tesslevel_declaration
5550 VGPU10OperandToken0 operand0; local in function:emit_constant_declaration
5657 VGPU10OperandToken0 operand0; local in function:emit_sampler_declarations
5815 VGPU10OperandToken0 operand0; local in function:emit_resource_declarations
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/nir_to_spirv/
H A Dspirv_builder.h205 SpvId operand0, SpvId operand1);
209 SpvId operand0, SpvId operand1, SpvId operand2);
213 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3);
217 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3,
H A Dspirv_builder.c506 SpvId operand0, SpvId operand1)
513 spirv_buffer_emit_word(&b->instructions, operand0);
520 SpvId operand0, SpvId operand1, SpvId operand2)
527 spirv_buffer_emit_word(&b->instructions, operand0);
535 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3)
542 spirv_buffer_emit_word(&b->instructions, operand0);
551 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3,
559 spirv_buffer_emit_word(&b->instructions, operand0);
505 spirv_builder_emit_binop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1) argument
519 spirv_builder_emit_triop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2) argument
534 spirv_builder_emit_quadop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2,SpvId operand3) argument
550 spirv_builder_emit_hexop(struct spirv_builder * b,SpvOp op,SpvId result_type,SpvId operand0,SpvId operand1,SpvId operand2,SpvId operand3,SpvId operand4,SpvId operand5) argument

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