Searched refs:processors (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_threads.c110 uint32_t processors = 0, cores = 0; local in function:num_cores
116 processors |= 1 << id;
126 DBG(("%s: processors=0x%08x, cores=0x%08x\n",
127 __FUNCTION__, processors, cores));
129 count = popcount(processors) * popcount(cores);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_threads.c110 uint32_t processors = 0, cores = 0; local in function:num_cores
116 processors |= 1 << id;
126 DBG(("%s: processors=0x%08x, cores=0x%08x\n",
127 __FUNCTION__, processors, cores));
129 count = popcount(processors) * popcount(cores);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_256_avx512_core.inl28 // SIMD256 AVX (512) implementation for Core processors
H A Dsimdlib_512_avx512_core.inl28 // SIMD16 AVX512 (F) implementation for Core processors
H A Dsimdlib_512_avx512.inl45 // processors)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_256_avx512_core.inl28 // SIMD256 AVX (512) implementation for Core processors
H A Dsimdlib_512_avx512_core.inl28 // SIMD16 AVX512 (F) implementation for Core processors
H A Dsimdlib_512_avx512.inl45 // processors)
/xsrc/external/mit/MesaLib/dist/docs/drivers/
H A Dllvmpipe.rst17 - For x86 or amd64 processors, 64-bit mode is recommended. Support for
23 For ppc64le processors, use of the Altivec feature (the Vector

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