Searched refs:qmd (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dqmdc3c0.c22 #include "qmd.h"
30 NVC3C0QmdDump_V02_02(uint32_t *qmd) argument
32 NVC3C0_QMDV02_02_VAL(qmd, OUTER_PUT, "0x%x");
33 NVC3C0_QMDV02_02_VAL(qmd, OUTER_OVERFLOW, "0x%x");
34 NVC3C0_QMDV02_02_VAL(qmd, OUTER_GET, "0x%x");
35 NVC3C0_QMDV02_02_VAL(qmd, OUTER_STICKY_OVERFLOW, "0x%x");
36 NVC3C0_QMDV02_02_VAL(qmd, INNER_GET, "0x%x");
37 NVC3C0_QMDV02_02_VAL(qmd, INNER_OVERFLOW, "0x%x");
38 NVC3C0_QMDV02_02_VAL(qmd, INNER_PUT, "0x%x");
39 NVC3C0_QMDV02_02_VAL(qmd, INNER_STICKY_OVERFLO
[all...]
H A Dqmdc0c0.c22 #include "qmd.h"
30 NVC0C0QmdDump_V02_01(uint32_t *qmd) argument
32 NVC0C0_QMDV02_01_VAL(qmd, OUTER_PUT, "0x%x");
33 NVC0C0_QMDV02_01_VAL(qmd, OUTER_OVERFLOW, "0x%x");
34 NVC0C0_QMDV02_01_VAL(qmd, OUTER_GET, "0x%x");
35 NVC0C0_QMDV02_01_VAL(qmd, OUTER_STICKY_OVERFLOW, "0x%x");
36 NVC0C0_QMDV02_01_VAL(qmd, INNER_GET, "0x%x");
37 NVC0C0_QMDV02_01_VAL(qmd, INNER_OVERFLOW, "0x%x");
38 NVC0C0_QMDV02_01_VAL(qmd, INNER_PUT, "0x%x");
39 NVC0C0_QMDV02_01_VAL(qmd, INNER_STICKY_OVERFLO
[all...]
H A Dqmda0c0.c22 #include "qmd.h"
30 NVA0C0QmdDump_V00_06(uint32_t *qmd) argument
32 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_A, "0x%x");
33 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_B, "0x%x");
34 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_C, "0x%x");
35 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_D, "0x%x");
36 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_E, "0x%x");
37 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_F, "0x%x");
38 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_G, "0x%x");
39 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_
[all...]
H A Dnve4_compute.c31 #include "qmd.h"
570 gp100_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, argument
578 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
579 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
580 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index,
582 NVC0C0_QMDV02_01_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);
586 nve4_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, struct nouveau_bo *bo, argument
594 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
595 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
596 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_SIZ
625 nve4_compute_setup_launch_desc(struct nvc0_context * nvc0,uint32_t * qmd,const struct pipe_grid_info * info) argument
690 gp100_compute_setup_launch_desc(struct nvc0_context * nvc0,uint32_t * qmd,const struct pipe_grid_info * info) argument
750 gv100_compute_setup_launch_desc(struct nvc0_context * nvc0,u32 * qmd,const struct pipe_grid_info * info) argument
[all...]

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