Searched refs:qpu_insts (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_emit.c39 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
40 vc4_qpu_disasm(&c->qpu_insts[i], 1);
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
636 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
638 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
644 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
646 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
652 if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1]))
658 if (QPU_GET_FIELD(c->qpu_insts[
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H A Dvc4_qpu_schedule.c843 uint64_t prev_instr = c->qpu_insts[c->qpu_inst_count - i];
852 c->qpu_insts[thrsw_ip] =
853 QPU_UPDATE_FIELD(c->qpu_insts[thrsw_ip], sig, QPU_SIG);
1053 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
1128 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
H A Dvc4_qpu.c735 c->qpu_insts = reralloc(c, c->qpu_insts,
738 c->qpu_insts[c->qpu_inst_count++] = inst;
H A Dvc4_qir.h484 uint64_t *qpu_insts; member in struct:vc4_compile
H A Dvc4_program.c2608 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_qpu_emit.c39 fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
40 vc4_qpu_disasm(&c->qpu_insts[i], 1);
632 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
634 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
636 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
638 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
644 if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
646 QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
652 if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1]))
658 if (QPU_GET_FIELD(c->qpu_insts[
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H A Dvc4_qpu_schedule.c843 uint64_t prev_instr = c->qpu_insts[c->qpu_inst_count - i];
852 c->qpu_insts[thrsw_ip] =
853 QPU_UPDATE_FIELD(c->qpu_insts[thrsw_ip], sig, QPU_SIG);
1053 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
1128 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
H A Dvc4_qpu.c735 c->qpu_insts = reralloc(c, c->qpu_insts,
738 c->qpu_insts[c->qpu_inst_count++] = inst;
H A Dvc4_qir.h480 uint64_t *qpu_insts; member in struct:vc4_compile
H A Dvc4_program.c2633 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dvir_to_qpu.c377 const char *str = v3d_qpu_disasm(c->devinfo, c->qpu_insts[i]);
378 fprintf(stderr, "0x%016"PRIx64" %s", c->qpu_insts[i], str);
384 reads_uniform(c->devinfo, c->qpu_insts[i])) {
415 c->qpu_insts = rzalloc_array(c, uint64_t, c->qpu_inst_count);
419 &c->qpu_insts[i++]);
H A Dvir.c868 uint64_t *qpu_insts = malloc(*final_assembly_size); local in function:v3d_return_qpu_insts
869 if (!qpu_insts)
872 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
876 return qpu_insts;
H A Dv3d_compiler.h822 uint64_t *qpu_insts; member in struct:v3d_compile
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dvir_to_qpu.c372 const char *str = v3d_qpu_disasm(c->devinfo, c->qpu_insts[i]);
373 fprintf(stderr, "0x%016"PRIx64" %s", c->qpu_insts[i], str);
379 reads_uniform(c->devinfo, c->qpu_insts[i])) {
410 c->qpu_insts = rzalloc_array(c, uint64_t, c->qpu_inst_count);
414 &c->qpu_insts[i++]);
H A Dvir.c725 uint64_t *qpu_insts = malloc(*final_assembly_size); local in function:v3d_return_qpu_insts
726 if (!qpu_insts)
729 memcpy(qpu_insts, c->qpu_insts, *final_assembly_size);
733 return qpu_insts;
H A Dv3d_compiler.h603 uint64_t *qpu_insts; member in struct:v3d_compile
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
H A Dv3d_program.c351 uint64_t *qpu_insts; local in function:v3d_get_compiled_shader
354 qpu_insts = v3d_compile(v3d->screen->compiler, key,
365 qpu_insts, &shader->offset, &shader->resource);
368 free(qpu_insts);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/v3d/
H A Dv3d_program.c389 uint64_t *qpu_insts; local in function:v3d_get_compiled_shader
392 qpu_insts = v3d_compile(v3d->screen->compiler, key,
403 qpu_insts, &shader->offset, &shader->resource);
406 free(qpu_insts);
/xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
H A Dv3dv_pipeline.c1463 memcpy(bo->map + offset, variant->qpu_insts, variant->qpu_insts_size);
1466 /* We dont need qpu_insts anymore. */
1467 free(variant->qpu_insts);
1468 variant->qpu_insts = NULL;
1565 * Creation doesn't include allocate a BD to store the content of qpu_insts,
1577 uint64_t *qpu_insts,
1596 variant->qpu_insts = qpu_insts;
1641 uint64_t *qpu_insts; local in function:pipeline_compile_shader_variant
1647 qpu_insts
1572 v3dv_shader_variant_create(struct v3dv_device * device,enum broadcom_shader_stage stage,struct v3d_prog_data * prog_data,uint32_t prog_data_size,uint32_t assembly_offset,uint64_t * qpu_insts,uint32_t qpu_insts_size,VkResult * out_vk_result) argument
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H A Dv3dv_private.h1434 /* Note: it is really likely that qpu_insts would be NULL, as it will be
1438 uint64_t *qpu_insts; member in struct:v3dv_shader_variant
1917 uint64_t *qpu_insts,

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