Searched refs:rad_info (Results 1 - 25 of 44) sorted by relevance

12

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_sqtt.c39 ac_thread_trace_get_data_offset(const struct radeon_info *rad_info, argument
42 unsigned max_se = rad_info->max_se;
59 ac_thread_trace_get_data_va(const struct radeon_info *rad_info, argument
62 return va + ac_thread_trace_get_data_offset(rad_info, data, se);
66 ac_is_thread_trace_complete(struct radeon_info *rad_info, argument
70 if (rad_info->chip_class >= GFX10) {
90 ac_get_expected_buffer_size(struct radeon_info *rad_info, argument
93 if (rad_info->chip_class >= GFX10) {
94 uint32_t dropped_cntr_per_se = info->gfx10_dropped_cntr / rad_info->max_se;
H A Dac_rgp.c438 static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, argument
441 bool has_wave32 = rad_info->chip_class >= GFX10;
454 if (rad_info->chip_class < GFX9)
458 if (rad_info->family == CHIP_FIJI || rad_info->chip_class >= GFX9)
461 chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000;
462 chunk->trace_memory_clock = rad_info->max_memory_clock * 1000000;
471 chunk->device_id = rad_info->pci_id;
472 chunk->device_revision_id = rad_info->pci_rev_id;
473 chunk->vgprs_per_simd = rad_info
828 ac_sqtt_dump_data(struct radeon_info * rad_info,struct ac_thread_trace * thread_trace,FILE * output) argument
[all...]
H A Dac_sqtt.h82 ac_thread_trace_get_data_offset(const struct radeon_info *rad_info,
88 ac_thread_trace_get_data_va(const struct radeon_info *rad_info,
92 ac_is_thread_trace_complete(struct radeon_info *rad_info,
97 ac_get_expected_buffer_size(struct radeon_info *rad_info,
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_sqtt.c42 return device->physical_device->rad_info.cu_mask[se][0] == 0;
54 if (device->physical_device->rad_info.chip_class == GFX10_3)
65 struct radeon_info *rad_info = &device->physical_device->rad_info; local in function:radv_emit_thread_trace_start
66 unsigned max_se = rad_info->max_se;
70 uint64_t data_va = ac_thread_trace_get_data_va(rad_info, &device->thread_trace, va, se);
72 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]);
82 if (device->physical_device->rad_info.chip_class >= GFX10) {
134 if (device->physical_device->rad_info.chip_class < GFX9) {
153 if (device->physical_device->rad_info
622 struct radeon_info *rad_info = &device->physical_device->rad_info; local in function:radv_get_thread_trace
[all...]
H A Dsi_cmd_buffer.c40 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 ac_get_harvested_configs(&physical_device->rad_info, raster_config, &raster_config_1,
49 if (physical_device->rad_info.chip_class < GFX7)
61 if (physical_device->rad_info.chip_class < GFX7)
70 if (physical_device->rad_info.chip_class >= GFX7)
83 S_00B834_DATA(device->physical_device->rad_info.address32_hi >> 8));
91 if (device->physical_device->rad_info.chip_class >= GFX7) {
106 if (device->physical_device->rad_info.chip_class >= GFX9) {
108 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
111 if (device->physical_device->rad_info
[all...]
H A Dradv_image.c59 device->physical_device->rad_info.chip_class <= GFX8) {
77 if (device->physical_device->rad_info.chip_class < GFX8)
93 if (device->physical_device->rad_info.chip_class < GFX9) {
117 if (device->physical_device->rad_info.chip_class >= GFX9)
237 if (device->physical_device->rad_info.chip_class < GFX8)
254 (device->physical_device->rad_info.chip_class < GFX10 ||
276 if (device->physical_device->rad_info.chip_class < GFX10) {
283 device->physical_device->rad_info.chip_class == GFX9)
324 return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.chip_class,
353 image->info.array_size == 1 && device->physical_device->rad_info
1363 struct radeon_info *rad_info = &device->physical_device->rad_info; local in function:radv_image_is_pipe_misaligned
[all...]
H A Dradv_shader.c86 .lower_iadd_sat = device->rad_info.chip_class <= GFX8,
89 .has_dot_4x8 = device->rad_info.has_accelerated_dot_product,
90 .has_dot_2x16 = device->rad_info.has_accelerated_dot_product,
271 nir_ssa_def *comp[] = {ptr, nir_imm_int(b, pdev->rad_info.address32_hi)};
475 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
515 .fragment_shading_rate = device->physical_device->rad_info.chip_class >= GFX10_3,
606 if (device->physical_device->rad_info.chip_class == GFX6) {
666 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
751 if (ac_nir_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class) &&
855 ac_nir_lower_es_outputs_to_mem(nir, device->physical_device->rad_info
[all...]
H A Dradv_debug.c85 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, &device->dmesg_timestamp,
116 ac_dump_reg(f, device->physical_device->rad_info.chip_class, offset, value, ~0);
122 struct radeon_info *info = &device->physical_device->rad_info;
196 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
371 enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
588 struct radeon_info *info = &device->physical_device->rad_info;
621 device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx");
639 device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx");
668 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
779 ac_print_gpu_info(&device->physical_device->rad_info,
[all...]
H A Dradv_device.c158 return MIN2(device->rad_info.vram_size, (uint64_t)ov << 20);
159 return device->rad_info.vram_size;
165 return MIN2(radv_get_adjusted_vram_size(device), device->rad_info.vram_vis_size);
172 return total_size - MIN2(total_size, device->rad_info.vram_vis_size);
187 uint64_t gtt_size = device->rad_info.gart_size;
193 if (!device->rad_info.has_dedicated_vram) {
199 visible_vram_size = align64((total_size * 2) / 3, device->rad_info.gart_page_size);
275 if (device->rad_info.has_l2_uncached) {
428 .KHR_fragment_shading_rate = device->rad_info.chip_class >= GFX10_3,
475 .EXT_conservative_rasterization = device->rad_info
[all...]
H A Dradv_cs.h123 if (pdevice->rad_info.chip_class < GFX10)
167 if (pdevice->rad_info.chip_class < GFX9 ||
168 (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26))
H A Dradv_pipeline.c255 MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_good_compute_units *
424 bool use_rbplus = device->physical_device->rad_info.rbplus_allowed;
763 if (pipeline->device->physical_device->rad_info.has_rbplus) {
1032 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1104 pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1141 pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1406 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
1425 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
1426 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
1427 device->physical_device->rad_info
[all...]
H A Dradv_formats.c161 if (pdevice->rad_info.chip_class <= GFX8 && pdevice->rad_info.family != CHIP_STONEY) {
602 return physical_device->rad_info.chip_class >= GFX10_3;
643 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 && pdevice->rad_info.chip_class < GFX10_3)
688 return physical_device->rad_info.family == CHIP_VEGA10 ||
689 physical_device->rad_info.family == CHIP_RAVEN ||
690 physical_device->rad_info.family == CHIP_RAVEN2 ||
691 physical_device->rad_info.family == CHIP_STONEY;
1240 ac_get_supported_modifiers(&dev->rad_info, &radv_modifier_options,
1255 ac_get_supported_modifiers(&dev->rad_info,
[all...]
H A Dradv_wsi.c60 physical_device->wsi_device.supports_modifiers = physical_device->rad_info.chip_class >= GFX9;
H A Dradv_cmd_buffer.c374 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
531 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
533 unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends;
545 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
616 struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info; local in function:radv_cmd_buffer_upload_alloc
622 unsigned line_size = rad_info->chip_class >= GFX10 ? 64 : 32;
691 cmd_buffer->device->physical_device->rad_info.chip_class,
1046 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
1055 if (cmd_buffer->device->physical_device->rad_info
6664 const struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info; local in function:radv_after_draw
[all...]
H A Dradv_meta_dcc_retile.c64 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe,
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
H A Dradv_query.c144 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
145 unsigned db_count = device->physical_device->rad_info.max_render_backends;
937 pool->stride = 16 * device->physical_device->rad_info.max_render_backends;
1039 uint32_t db_count = device->physical_device->rad_info.max_render_backends;
1040 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
1243 unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask;
1535 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,
1578 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1681 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,
1693 if (cmd_buffer->device->physical_device->rad_info
[all...]
H A Dradv_meta_bufimage.c103 if (device->physical_device->rad_info.chip_class >= GFX9)
170 if (device->physical_device->rad_info.chip_class >= GFX9) {
212 if (device->physical_device->rad_info.chip_class >= GFX9)
287 if (device->physical_device->rad_info.chip_class >= GFX9)
353 if (device->physical_device->rad_info.chip_class >= GFX9) {
704 if (device->physical_device->rad_info.chip_class >= GFX9) {
747 if (device->physical_device->rad_info.chip_class >= GFX9)
1023 if (device->physical_device->rad_info.chip_class >= GFX9) {
1252 VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9
1358 if (cmd_buffer->device->physical_device->rad_info
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c44 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
48 ac_get_harvested_configs(&physical_device->rad_info,
55 if (physical_device->rad_info.chip_class < CIK)
68 if (physical_device->rad_info.chip_class < CIK)
78 if (physical_device->rad_info.chip_class >= CIK)
96 if (physical_device->rad_info.chip_class >= CIK) {
111 if (physical_device->rad_info.chip_class <= SI) {
131 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
132 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 ac_get_raster_config(&physical_device->rad_info,
[all...]
H A Dradv_device.c127 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
133 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
158 if (device->rad_info.gart_size > 0) {
161 .size = device->rad_info.gart_size,
162 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
180 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
218 device->rad_info.family = i;
221 device->rad_info
[all...]
H A Dradv_pipeline.c158 4 * device->physical_device->rad_info.num_good_compute_units *
1072 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1121 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1442 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1561 unsigned num_se = device->physical_device->rad_info.max_se;
1568 (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se;
1587 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1605 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1606 device->physical_device->rad_info.family == CHIP_KABINI ||
1607 device->physical_device->rad_info
[all...]
H A Dradv_image.c50 && device->physical_device->rad_info.chip_class <= VI) {
72 if (device->physical_device->rad_info.chip_class < VI)
133 if (device->physical_device->rad_info.chip_class < VI)
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
257 if (device->physical_device->rad_info.chip_class >= GFX9 &&
275 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
331 if (device->physical_device->rad_info.chip_class != VI && stride) {
356 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
530 if (device->physical_device->rad_info.chip_class >= GFX9 &&
539 is_storage_image, device->physical_device->rad_info
[all...]
H A Dradv_shader.c374 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
480 if (device->physical_device->rad_info.chip_class >= GFX9) {
507 if (device->physical_device->rad_info.chip_class >= GFX9 &&
536 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
603 enum radeon_family chip_family = device->physical_device->rad_info.family;
614 options->chip_class = device->physical_device->rad_info.chip_class;
621 options->address32_hi = device->physical_device->rad_info.address32_hi;
754 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
760 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
857 unsigned lds_multiplier = device->physical_device->rad_info
[all...]
H A Dradv_debug.c77 ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
106 ac_dump_reg(f, device->physical_device->rad_info.chip_class,
113 struct radeon_info *info = &device->physical_device->rad_info;
319 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
631 struct radeon_info *info = &device->physical_device->rad_info;
673 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
H A Dradv_meta_bufimage.c138 if (device->physical_device->rad_info.chip_class >= GFX9)
214 if (device->physical_device->rad_info.chip_class >= GFX9) {
259 if (device->physical_device->rad_info.chip_class >= GFX9)
364 if (device->physical_device->rad_info.chip_class >= GFX9)
439 if (device->physical_device->rad_info.chip_class >= GFX9) {
788 if (device->physical_device->rad_info.chip_class >= GFX9)
863 if (device->physical_device->rad_info.chip_class >= GFX9) {
907 if (device->physical_device->rad_info.chip_class >= GFX9)
1194 if (device->physical_device->rad_info.chip_class >= GFX9)
1264 if (device->physical_device->rad_info
[all...]
H A Dradv_formats.c625 return physical_device->rad_info.family == CHIP_VEGA10 ||
626 physical_device->rad_info.family == CHIP_RAVEN ||
627 physical_device->rad_info.family == CHIP_STONEY;
765 if (physical_device->rad_info.chip_class <= VI &&
766 physical_device->rad_info.family != CHIP_STONEY) {
1186 if (physical_device->rad_info.chip_class >= GFX9 &&

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