Searched refs:radeon_emit (Results 1 - 25 of 93) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dcayman_msaa.c168 radeon_emit(cs, cm_sample_locs_8x[0]);
169 radeon_emit(cs, cm_sample_locs_8x[4]);
170 radeon_emit(cs, 0);
171 radeon_emit(cs, 0);
172 radeon_emit(cs, cm_sample_locs_8x[1]);
173 radeon_emit(cs, cm_sample_locs_8x[5]);
174 radeon_emit(cs, 0);
175 radeon_emit(cs, 0);
176 radeon_emit(cs, cm_sample_locs_8x[2]);
177 radeon_emit(c
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H A Devergreen_hw_context.c69 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize));
70 radeon_emit(cs, dst_offset & 0xffffffff);
71 radeon_emit(cs, src_offset & 0xffffffff);
72 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
130 radeon_emit(cs, clear_value); /* DATA [31:0] */
131 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
132 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */
133 radeon_emit(c
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H A Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
126 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
131 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
145 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
151 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
165 radeon_emit(c
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H A Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
127 radeon_emit(cs, reloc);
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
142 radeon_emit(cs, value);
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
156 radeon_emit(cs, value);
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
166 radeon_emit(c
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H A Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
170 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
173 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
174 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
175 radeon_emit(cs, 0);
176 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
177 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
178 radeon_emit(cs, 4); /* poll interval */
201 radeon_emit(c
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dcayman_msaa.c168 radeon_emit(cs, cm_sample_locs_8x[0]);
169 radeon_emit(cs, cm_sample_locs_8x[4]);
170 radeon_emit(cs, 0);
171 radeon_emit(cs, 0);
172 radeon_emit(cs, cm_sample_locs_8x[1]);
173 radeon_emit(cs, cm_sample_locs_8x[5]);
174 radeon_emit(cs, 0);
175 radeon_emit(cs, 0);
176 radeon_emit(cs, cm_sample_locs_8x[2]);
177 radeon_emit(c
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H A Devergreen_hw_context.c69 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize));
70 radeon_emit(cs, dst_offset & 0xffffffff);
71 radeon_emit(cs, src_offset & 0xffffffff);
72 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
130 radeon_emit(cs, clear_value); /* DATA [31:0] */
131 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
132 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */
133 radeon_emit(c
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H A Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
126 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
131 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
145 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
151 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
165 radeon_emit(c
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H A Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
127 radeon_emit(cs, reloc);
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
142 radeon_emit(cs, value);
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
156 radeon_emit(cs, value);
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
166 radeon_emit(c
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H A Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
170 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
173 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
174 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
175 radeon_emit(cs, 0);
176 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
177 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
178 radeon_emit(cs, 4); /* poll interval */
201 radeon_emit(c
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
56 radeon_emit(cs, value);
65 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
66 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
73 radeon_emit(cs, value);
81 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
82 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
83 radeon_emit(cs, value);
91 radeon_emit(c
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H A Dsi_cmd_buffer.c78 radeon_emit(cs, 0);
79 radeon_emit(cs, 0);
80 radeon_emit(cs, 0);
88 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
89 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, bc_va >> 8);
102 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40));
113 radeon_emit(c
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H A Dradv_sqtt.c184 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
185 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_START) | EVENT_INDEX(0));
228 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
229 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | COPY_DATA_DST_SEL(COPY_DATA_TC_L2) |
231 radeon_emit(cs, thread_trace_info_regs[i] >> 2);
232 radeon_emit(cs, 0); /* unused */
233 radeon_emit(cs, (info_va + i * 4));
234 radeon_emit(cs, (info_va + i * 4) >> 32);
249 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
250 radeon_emit(c
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
54 radeon_emit(cs, value);
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
69 radeon_emit(cs, value);
79 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
80 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
81 radeon_emit(cs, value);
89 radeon_emit(c
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H A Dsi_cmd_buffer.c87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89 radeon_emit(cs, 0);
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
100 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
102 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
165 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
166 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
167 radeon_emit(c
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H A Dradv_cmd_buffer.c462 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
463 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
466 radeon_emit(cs, va);
467 radeon_emit(cs, va >> 32);
487 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
488 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
667 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
668 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
676 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
677 radeon_emit(cmd_buffe
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h39 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
40 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
46 radeon_emit(cs, value);
53 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
54 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
60 radeon_emit(cs, value);
69 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
70 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
71 radeon_emit(cs, value);
78 radeon_emit(c
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H A Dsi_state_streamout.c206 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
207 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
209 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
210 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
211 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
212 radeon_emit(cs, 0);
213 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
214 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
215 radeon_emit(cs, 4); /* poll interval */
237 radeon_emit(c
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H A Dcik_sdma.c55 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
58 radeon_emit(cs, ctx->chip_class >= GFX9 ? csize - 1 : csize);
59 radeon_emit(cs, 0); /* src/dst endian swap */
60 radeon_emit(cs, src_offset);
61 radeon_emit(cs, src_offset >> 32);
62 radeon_emit(cs, dst_offset);
63 radeon_emit(cs, dst_offset >> 32);
197 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
200 radeon_emit(cs, src_address);
201 radeon_emit(c
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H A Dsi_state_draw.c264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
292 radeon_emit(c
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H A Dsi_dma_cs.c34 radeon_emit(cs, 0x00000000); /* NOP */
36 radeon_emit(cs, 0xf0000000); /* NOP */
60 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_TIMESTAMP,
63 radeon_emit(cs, va);
64 radeon_emit(cs, va >> 32);
97 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0,
99 radeon_emit(cs, offset);
100 radeon_emit(cs, clear_value);
101 radeon_emit(cs, (offset >> 32) << 16);
115 radeon_emit(c
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h61 #define radeon_emit(value) __cs_buf[__cs_num++] = (value) macro
79 radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
80 radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
85 radeon_emit(value); \
91 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
92 radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
97 radeon_emit(value); \
108 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
109 radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2 | ((idx) << 28)); \
110 radeon_emit(valu
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H A Dsi_sdma_copy_image.c139 radeon_emit(CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
142 radeon_emit(bytes);
143 radeon_emit(0);
144 radeon_emit(src_address);
145 radeon_emit(src_address >> 32);
146 radeon_emit(dst_address);
147 radeon_emit(dst_address >> 32);
176 radeon_emit(
183 radeon_emit((uint32_t)tiled_address | (tiled->surface.tile_swizzle << 8));
184 radeon_emit((uint32_
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H A Dsi_state_streamout.c243 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0));
244 radeon_emit(S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
246 radeon_emit(va);
247 radeon_emit(va >> 32);
248 radeon_emit(4 * i); /* destination in GDS */
249 radeon_emit(0);
250 radeon_emit(S_415_BYTE_COUNT_GFX9(4) | S_415_DISABLE_WR_CONFIRM_GFX9(i != last_target));
293 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
294 radeon_emit(EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
296 radeon_emit(PKT
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H A Dsi_gfx_cs.c553 radeon_emit(PKT3(PKT3_NOP, 0, 0));
554 radeon_emit(AC_ENCODE_TRACE_POINT(trace_id));
575 radeon_emit(PKT3(PKT3_ACQUIRE_MEM, 5, 0));
576 radeon_emit(cp_coher_cntl); /* CP_COHER_CNTL */
577 radeon_emit(0xffffffff); /* CP_COHER_SIZE */
578 radeon_emit(0xffffff); /* CP_COHER_SIZE_HI */
579 radeon_emit(0); /* CP_COHER_BASE */
580 radeon_emit(0); /* CP_COHER_BASE_HI */
581 radeon_emit(0x0000000A); /* POLL_INTERVAL */
584 radeon_emit(PKT
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