Searched refs:radeon_opt_set_context_reg (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_binning.c315 radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
319 radeon_opt_set_context_reg(sctx, R_028060_DB_DFSM_CONTROL,
428 radeon_opt_set_context_reg(
441 radeon_opt_set_context_reg(sctx, R_028060_DB_DFSM_CONTROL,
H A Dsi_state_shaders.c564 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
574 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
780 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
785 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
799 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
805 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
809 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
813 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
818 radeon_opt_set_context_reg(sct
[all...]
H A Dsi_state_viewport.c275 radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
279 radeon_opt_set_context_reg(ctx, R_028BE4_PA_SU_VTX_CNTL,
564 radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE,
H A Dsi_build_pm4.h120 static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset, function in typeref:typename:void
H A Dsi_state.c103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
118 radeon_opt_set_context_reg(
783 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
789 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
1428 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1450 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
3322 radeon_opt_set_context_reg(sctx,
3333 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3536 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3539 radeon_opt_set_context_reg(sct
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_binning.c421 radeon_opt_set_context_reg(
429 radeon_opt_set_context_reg(
506 radeon_opt_set_context_reg(
H A Dsi_state_shaders.c611 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
616 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
620 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
781 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
786 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
797 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
805 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
809 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
814 radeon_opt_set_context_reg(sct
[all...]
H A Dsi_state_viewport.c363 radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
367 radeon_opt_set_context_reg(
641 radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE,
H A Dsi_build_pm4.h156 #define radeon_opt_set_context_reg(sctx, offset, reg, val) do { \ macro
H A Dsi_state.c103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
115 radeon_opt_set_context_reg(
856 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
858 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
1498 radeon_opt_set_context_reg(
1520 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1525 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
1540 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
3456 radeon_opt_set_context_reg(sctx, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3464 radeon_opt_set_context_reg(
[all...]
H A Dsi_state_draw.cpp1075 radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE, SI_TRACKED_PA_SC_LINE_STIPPLE,

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