Searched refs:radeon_set_config_reg (Results 1 - 25 of 31) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dsi_cmd_buffer.c56 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
197 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dsi_cmd_buffer.c50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
133 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
222 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_cs.h139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dr600_state.c1296 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1300 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1659 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1660 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1896 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1965 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1971 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1976 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1980 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1985 radeon_set_config_reg(c
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H A Dr600_hw_context.c138 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
569 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
H A Devergreen_compute.c611 radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size);
618 radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE,
777 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
H A Dr600_streamout.c167 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
H A Dr600_state_common.c1659 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1670 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1677 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1683 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1688 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1695 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2257 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2376 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
H A Devergreen_state.c990 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
2672 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2678 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2684 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2688 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2694 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2697 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2698 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2701 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h43 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dsi_state_streamout.c203 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
H A Dsi_compute.c362 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
H A Dsi_state_draw.c640 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_cs.h139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dr600_state.c1299 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1303 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1662 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1663 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1899 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1968 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1974 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1979 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1983 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1988 radeon_set_config_reg(c
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H A Dr600_hw_context.c138 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
569 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
H A Devergreen_compute.c633 radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size);
640 radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE,
805 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
H A Dr600_streamout.c167 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
H A Dr600_state_common.c1718 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1729 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1736 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1742 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1747 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1754 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2337 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2456 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
H A Devergreen_state.c996 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
2678 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2684 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2690 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2694 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2700 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2703 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2704 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2707 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h83 #define radeon_set_config_reg(reg, value) do { \ macro
H A Dsi_state_streamout.c290 radeon_set_config_reg(reg_strmout_cntl, 0);
H A Dsi_compute.c392 radeon_set_config_reg(R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);

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