| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_cs.h | 42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
53 radeon_set_config_reg_seq(cs, reg, 1);
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| H A D | radv_device.c | 2321 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_cs.h | 43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
55 radeon_set_config_reg_seq(cs, reg, 1);
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| H A D | radv_device.c | 3599 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600_cs.h | 131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
141 radeon_set_config_reg_seq(cs, reg, 1);
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| H A D | evergreen_compute.c | 613 radeon_set_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3);
773 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
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| H A D | r600_state.c | 1304 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1862 radeon_set_config_reg_seq(cs, offset, 4);
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| H A D | evergreen_state.c | 980 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
2473 radeon_set_config_reg_seq(cs, border_index_reg, 5);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_build_pm4.h | 35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
45 radeon_set_config_reg_seq(cs, reg, 1);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600_cs.h | 131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
141 radeon_set_config_reg_seq(cs, reg, 1);
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| H A D | evergreen_compute.c | 635 radeon_set_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3);
801 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
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| H A D | r600_state.c | 1307 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1865 radeon_set_config_reg_seq(cs, offset, 4);
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| H A D | evergreen_state.c | 986 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
2479 radeon_set_config_reg_seq(cs, border_index_reg, 5);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_build_pm4.h | 76 #define radeon_set_config_reg_seq(reg, num) do { \ macro
84 radeon_set_config_reg_seq(reg, 1); \
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