Searched refs:radeon_set_context_reg (Results 1 - 25 of 37) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dcayman_msaa.c149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
162 radeon_set_context_reg(c
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H A Dr600_streamout.c284 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
318 radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
319 radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg, strmout_config_val);
H A Dr600_state.c281 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1382 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1395 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1408 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1467 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1473 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1491 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1496 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1532 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1542 radeon_set_context_reg(c
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H A Dr600_cs.h153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Devergreen_state.c992 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1690 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1698 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1776 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1854 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1905 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1912 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1914 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1927 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2009 radeon_set_context_reg(c
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dcayman_msaa.c149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
162 radeon_set_context_reg(c
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H A Dr600_streamout.c284 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
318 radeon_set_context_reg(&rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
319 radeon_set_context_reg(&rctx->gfx.cs, strmout_config_reg, strmout_config_val);
H A Dr600_state.c286 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1385 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1398 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1411 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1470 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1476 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1494 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1499 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1535 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1545 radeon_set_context_reg(c
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H A Dr600_cs.h153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Devergreen_state.c998 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1696 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1704 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1782 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1860 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1911 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1918 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1920 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1933 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2015 radeon_set_context_reg(c
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c64 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
79 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
143 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
177 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
179 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
183 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
184 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
188 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
189 radeon_set_context_reg(c
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H A Dradv_pipeline.c2700 radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
2702 radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
2778 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2779 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2781 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2782 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2783 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2794 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2795 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2803 radeon_set_context_reg(ctx_c
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H A Dradv_cs.h66 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
H A Dradv_cmd_buffer.c670 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
977 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1014 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1016 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1073 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1090 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1142 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1162 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1163 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1188 radeon_set_context_reg(cmd_buffe
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
173 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config);
175 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
201 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
203 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
207 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
208 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
212 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
213 radeon_set_context_reg(c
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H A Dradv_pipeline.c4281 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
4295 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
4303 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
4305 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
4337 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4352 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
4353 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
4364 radeon_set_context_reg(
4393 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
4394 radeon_set_context_reg(ctx_c
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H A Dradv_cmd_buffer.c967 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0,
969 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0,
971 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0,
973 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0,
977 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0,
979 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0,
981 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0,
983 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0,
985 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1,
987 radeon_set_context_reg(c
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H A Dradv_cs.h70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_msaa.c155 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs);
156 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs);
157 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs);
158 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs);
H A Dsi_build_pm4.h57 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) function in typeref:typename:void
127 radeon_set_context_reg(cs, offset, value);
H A Dsi_state_draw.c304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
560 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
631 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
651 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
658 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
682 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
H A Dsi_state_streamout.c305 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_msaa.c157 radeon_set_context_reg(R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs);
158 radeon_set_context_reg(R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs);
159 radeon_set_context_reg(R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs);
160 radeon_set_context_reg(R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs);
H A Dsi_build_pm4.h95 #define radeon_set_context_reg(reg, value) do { \ macro
160 radeon_set_context_reg(offset, __value); \
H A Dsi_state.c3059 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3154 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
3155 radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3157 radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3159 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
3160 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
3161 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
3200 radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4,
3266 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3302 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BAS
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