Searched refs:rb_depth_cntl (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_zsa.h40 uint32_t rb_depth_cntl; member in struct:fd5_zsa_stateobj
H A Dfd5_zsa.c68 so->rb_depth_cntl |=
72 so->rb_depth_cntl |=
77 so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
H A Dfd5_emit.c578 OUT_RING(ring, zsa->rb_depth_cntl);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_zsa.h39 uint32_t rb_depth_cntl; member in struct:fd5_zsa_stateobj
H A Dfd5_zsa.c68 so->rb_depth_cntl |=
72 so->rb_depth_cntl |=
76 so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
H A Dfd5_emit.c610 OUT_RING(ring, zsa->rb_depth_cntl);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_zsa.h41 uint32_t rb_depth_cntl; member in struct:fd6_zsa_stateobj
H A Dfd6_zsa.c75 so->rb_depth_cntl |=
79 so->rb_depth_cntl |=
84 so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
135 OUT_RING(ring, so->rb_depth_cntl);
151 OUT_RING(ring, so->rb_depth_cntl);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_zsa.c106 so->rb_depth_cntl |=
110 so->rb_depth_cntl |=
149 so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
218 so->rb_depth_cntl | COND(i & FD6_ZSA_DEPTH_CLAMP,
H A Dfd6_zsa.h45 uint32_t rb_depth_cntl; member in struct:fd6_zsa_stateobj
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c478 uint32_t *rb_depth_cntl)
489 *rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE |
2261 UPDATE_REG(rb_depth_cntl, RB_DEPTH_CNTL);
2472 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2475 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2486 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2489 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2500 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2502 cmd->state.rb_depth_cntl |=
2514 cmd->state.rb_depth_cntl
477 tu6_apply_depth_bounds_workaround(struct tu_device * device,uint32_t * rb_depth_cntl) argument
3908 uint32_t rb_depth_cntl = cmd->state.rb_depth_cntl; local in function:tu6_draw_common
[all...]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member in struct:tu_cmd_state
1209 uint32_t rb_depth_cntl, rb_depth_cntl_mask; member in struct:tu_pipeline
1298 uint32_t *rb_depth_cntl);
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; local in function:tu_pipeline_builder_parse_depth_stencil
2874 rb_depth_cntl |=
2880 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
2883 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2887 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
2890 tu6_apply_depth_bounds_workaround(builder->device, &rb_depth_cntl);
2924 tu_cs_emit(&cs, rb_depth_cntl);
2926 pipeline->rb_depth_cntl = rb_depth_cntl;
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
H A Dtu_pipeline.c1165 uint32_t rb_depth_cntl = 0; local in function:tu6_emit_depth_control
1167 rb_depth_cntl |=
1173 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1177 tu_cs_emit(cs, rb_depth_cntl);

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