Searched refs:rdst (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Devergreen_hw_context.c40 struct r600_resource *rdst = (struct r600_resource*)dst; local in function:evergreen_dma_copy_buffer
46 util_range_add(&rdst->b.b, &rdst->valid_buffer_range, dst_offset,
49 dst_offset += rdst->gpu_address;
63 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
68 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
H A Dr600_buffer_common.c272 struct r600_resource *rdst = r600_resource(dst); local in function:r600_replace_buffer_storage
274 uint64_t old_gpu_address = rdst->gpu_address;
276 pb_reference(&rdst->buf, rsrc->buf);
277 rdst->gpu_address = rsrc->gpu_address;
278 rdst->b.b.bind = rsrc->b.b.bind;
279 rdst->flags = rsrc->flags;
281 assert(rdst->vram_usage == rsrc->vram_usage);
282 assert(rdst->gart_usage == rsrc->gart_usage);
283 assert(rdst->bo_size == rsrc->bo_size);
284 assert(rdst
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H A Dr600_test_dma.c207 struct r600_texture *rdst; local in function:r600_test_dma
277 rdst = (struct r600_texture*)dst;
285 array_mode_to_string(rscreen, &rdst->surface),
294 rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
325 !rdst->surface.is_linear &&
353 !rdst->surface.is_linear &&
H A Dr600_hw_context.c589 struct r600_resource *rdst = (struct r600_resource*)dst; local in function:r600_dma_copy_buffer
595 util_range_add(&rdst->b.b, &rdst->valid_buffer_range, dst_offset,
601 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
606 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
H A Dr600_state.c2864 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:r600_dma_copy_tile
2869 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2893 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2894 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2899 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2906 height = u_minify(rdst->resource.b.b.height0, dst_level);
2911 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2926 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2933 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst
2960 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:r600_dma_copy
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H A Dr600_pipe_common.c1070 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst; local in function:r600_fence_reference
1073 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1074 ws->fence_reference(&(*rdst)->gfx, NULL);
1075 ws->fence_reference(&(*rdst)->sdma, NULL);
1076 FREE(*rdst);
1078 *rdst = rsrc;
H A Devergreen_state.c3786 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:evergreen_dma_copy_tile
3792 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3822 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3823 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3830 addr += rdst->resource.gpu_address;
3834 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3841 height = u_minify(rdst->resource.b.b.height0, dst_level);
3846 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3850 bank_h = eg_bank_wh(rdst
3900 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:evergreen_dma_copy
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H A Dr600_texture.c48 struct r600_texture *rdst,
58 if (rdst->surface.bpe != rsrc->surface.bpe)
63 rdst->resource.b.b.nr_samples > 1)
70 if (rsrc->is_depth || rdst->is_depth)
78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
81 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
86 r600_texture_discard_cmask(rctx->screen, rdst);
94 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
47 r600_prepare_for_dma_blit(struct r600_common_context * rctx,struct r600_texture * rdst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct r600_texture * rsrc,unsigned src_level,const struct pipe_box * src_box) argument
H A Dr600_blit.c624 struct r600_resource_global *rdst = local in function:r600_copy_global_buffer
626 struct compute_memory_item *item = rdst->chunk;
921 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource; local in function:r600_blit
933 if (rdst->surface.u.legacy.level[info->dst.level].mode ==
H A Dr600_pipe_common.h749 struct r600_texture *rdst,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Devergreen_hw_context.c40 struct r600_resource *rdst = (struct r600_resource*)dst; local in function:evergreen_dma_copy_buffer
46 util_range_add(&rdst->valid_buffer_range, dst_offset,
49 dst_offset += rdst->gpu_address;
63 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
68 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
H A Dr600_buffer_common.c274 struct r600_resource *rdst = r600_resource(dst); local in function:r600_replace_buffer_storage
276 uint64_t old_gpu_address = rdst->gpu_address;
278 pb_reference(&rdst->buf, rsrc->buf);
279 rdst->gpu_address = rsrc->gpu_address;
280 rdst->b.b.bind = rsrc->b.b.bind;
281 rdst->flags = rsrc->flags;
283 assert(rdst->vram_usage == rsrc->vram_usage);
284 assert(rdst->gart_usage == rsrc->gart_usage);
285 assert(rdst->bo_size == rsrc->bo_size);
286 assert(rdst
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H A Dr600_test_dma.c208 struct r600_texture *rdst; local in function:r600_test_dma
278 rdst = (struct r600_texture*)dst;
286 array_mode_to_string(rscreen, &rdst->surface),
295 rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
326 !rdst->surface.is_linear &&
354 !rdst->surface.is_linear &&
H A Dr600_hw_context.c589 struct r600_resource *rdst = (struct r600_resource*)dst; local in function:r600_dma_copy_buffer
595 util_range_add(&rdst->valid_buffer_range, dst_offset,
601 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
606 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
H A Dr600_state.c2860 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:r600_dma_copy_tile
2865 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2889 addr = rdst->surface.u.legacy.level[dst_level].offset;
2890 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2895 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2902 height = u_minify(rdst->resource.b.b.height0, dst_level);
2907 base = rdst->surface.u.legacy.level[dst_level].offset;
2922 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2929 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst
2956 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:r600_dma_copy
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H A Dr600_pipe_common.c1151 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst; local in function:r600_fence_reference
1154 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1155 ws->fence_reference(&(*rdst)->gfx, NULL);
1156 ws->fence_reference(&(*rdst)->sdma, NULL);
1157 FREE(*rdst);
1159 *rdst = rsrc;
H A Devergreen_state.c3773 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:evergreen_dma_copy_tile
3779 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3809 addr = rdst->surface.u.legacy.level[dst_level].offset;
3810 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3817 addr += rdst->resource.gpu_address;
3821 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3828 height = u_minify(rdst->resource.b.b.height0, dst_level);
3833 base = rdst->surface.u.legacy.level[dst_level].offset;
3837 bank_h = eg_bank_wh(rdst
3887 struct r600_texture *rdst = (struct r600_texture*)dst; local in function:evergreen_dma_copy
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H A Dr600_texture.c47 struct r600_texture *rdst,
57 if (rdst->surface.bpe != rsrc->surface.bpe)
62 rdst->resource.b.b.nr_samples > 1)
69 if (rsrc->is_depth || rdst->is_depth)
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
85 r600_texture_discard_cmask(rctx->screen, rdst);
93 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
46 r600_prepare_for_dma_blit(struct r600_common_context * rctx,struct r600_texture * rdst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct r600_texture * rsrc,unsigned src_level,const struct pipe_box * src_box) argument
H A Dr600_blit.c622 struct r600_resource_global *rdst = local in function:r600_copy_global_buffer
624 struct compute_memory_item *item = rdst->chunk;
919 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource; local in function:r600_blit
931 if (rdst->surface.u.legacy.level[info->dst.level].mode ==
H A Dr600_pipe_common.h748 struct r600_texture *rdst,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/nine/
H A Dnine_shader.c1393 struct ureg_dst rdst; local in function:tx_apply_dst0_modifiers
1398 rdst = _tx_dst_param(tx, &tx->insn.dst[0]);
1400 assert(rdst.File != TGSI_FILE_ADDRESS); /* this probably isn't possible */
1407 ureg_MUL(tx->ureg, rdst, ureg_src(tx->regs.tdst), ureg_imm1f(tx->ureg, f));
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/nine/
H A Dnine_shader.c1414 struct ureg_dst rdst; local in function:tx_apply_dst0_modifiers
1419 rdst = _tx_dst_param(tx, &tx->insn.dst[0]);
1421 assert(rdst.File != TGSI_FILE_ADDRESS); /* this probably isn't possible */
1428 ureg_MUL(tx->ureg, rdst, ureg_src(tx->regs.tdst), ureg_imm1f(tx->ureg, f));
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.0.0.rst1806 - winsys/amdgpu: rename rfence, rsrc, rdst -> afence, asrc, adst
1810 - radeonsi: rename rsrc -> ssrc, rdst -> sdst

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