Searched refs:readSeq (Results 1 - 25 of 29) sorted by relevance

12

/xsrc/external/mit/xf86-video-mga/dist/src/
H A Dmga_vga.c51 seq2 = hwp->readSeq(hwp, 0x02);
52 seq4 = hwp->readSeq(hwp, 0x04);
61 scrn = hwp->readSeq(hwp, 0x01);
125 scrn = hwp->readSeq(hwp, 0x01);
168 seq2 = hwp->readSeq(hwp, 0x02);
169 seq4 = hwp->readSeq(hwp, 0x04);
178 scrn = hwp->readSeq(hwp, 0x01);
232 scrn = hwp->readSeq(hwp, 0x01);
269 scrn = hwp->readSeq(hwp, 0x01);
333 save->Sequencer[i] = hwp->readSeq(hw
[all...]
/xsrc/external/mit/xf86-video-openchrome/dist/src/
H A Dvia_tv.c59 sr5a = hwp->readSeq(hwp, 0x5A);
67 sr12 = hwp->readSeq(hwp, 0x12);
70 sr13 = hwp->readSeq(hwp, 0x13);
193 sr5a = hwp->readSeq(hwp, 0x5A);
201 sr12 = hwp->readSeq(hwp, 0x12);
204 sr13 = hwp->readSeq(hwp, 0x13);
327 sr5a = hwp->readSeq(hwp, 0x5A);
335 sr12 = hwp->readSeq(hwp, 0x12);
338 sr13 = hwp->readSeq(hwp, 0x13);
440 sr5a = hwp->readSeq(hw
[all...]
H A Dvia_tmds.c283 sr5a = hwp->readSeq(hwp, 0x5A);
291 sr12 = hwp->readSeq(hwp, 0x12);
294 sr13 = hwp->readSeq(hwp, 0x13);
350 sr5a = hwp->readSeq(hwp, 0x5A);
358 sr12 = hwp->readSeq(hwp, 0x12);
361 sr13 = hwp->readSeq(hwp, 0x13);
482 sr5a = hwp->readSeq(hwp, 0x5A);
490 sr12 = hwp->readSeq(hwp, 0x12);
493 sr13 = hwp->readSeq(hwp, 0x13);
613 sr5a = hwp->readSeq(hw
[all...]
H A Dvia_display.c887 temp = hwp->readSeq(hwp, 0x15);
890 temp = hwp->readSeq(hwp, 0x19);
893 temp = hwp->readSeq(hwp, 0x1A);
896 temp = hwp->readSeq(hwp, 0x1E);
899 temp = hwp->readSeq(hwp, 0x2D);
902 temp = hwp->readSeq(hwp, 0x2E);
905 temp = hwp->readSeq(hwp, 0x3F);
1170 temp = hwp->readSeq(hwp, 0x1B);
1173 temp = hwp->readSeq(hwp, 0x2D);
2054 Regs->SR[0x14] = hwp->readSeq(hw
[all...]
H A Dvia_vgahw.c113 tmp = hwp->readSeq(hwp, index);
144 "SR%02X: 0x%02X\n", i, hwp->readSeq(hwp, i));
H A Dvia_i2c.c64 CARD8 value = hwp->readSeq(hwp, 0x26);
138 CARD8 value = hwp->readSeq(hwp, 0x31);
283 if (hwp->readSeq(hwp, 0x2C) & 0x04)
306 if (hwp->readSeq(hwp, 0x2C) & 0x04)
363 CARD8 value = hwp->readSeq(hwp, 0x2C);
H A Dvia_outputs.c442 sr5a = hwp->readSeq(hwp, 0x5A);
450 sr12 = hwp->readSeq(hwp, 0x12);
453 sr13 = hwp->readSeq(hwp, 0x13);
612 sr12 = hwp->readSeq(hwp, 0x12);
615 sr13 = hwp->readSeq(hwp, 0x13);
H A Dvia_analog.c299 CARD8 SR01 = hwp->readSeq(hwp, 0x01);
300 CARD8 SR40 = hwp->readSeq(hwp, 0x40);
H A Dvia_fp.c457 sr5a = hwp->readSeq(hwp, 0x5A);
465 sr12 = hwp->readSeq(hwp, 0x12);
468 sr13 = hwp->readSeq(hwp, 0x13);
H A Dvia_ums.c845 bMemSize = hwp->readSeq(hwp, 0x39);
/xsrc/external/mit/xf86-video-cirrus/dist/src/
H A Dalp_i2c.c77 reg = hwp->readSeq(hwp, 0x08);
H A Dalp_driver.c281 pCir->chip.alp->sr0f = hwp->readSeq(hwp, 0x0F);
324 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
350 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
1138 pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1144 pCir->chip.alp->ModeReg.ExtVga[SR21] = pCir->chip.alp->SavedReg.ExtVga[SR21] = hwp->readSeq(hw
[all...]
H A Dlg_driver.c323 SR14 = hwp->readSeq(hwp, 0x14);
326 hwp->readSeq(hwp, 9),
327 hwp->readSeq(hwp, 10),
329 hwp->readSeq(hwp, 0x15));
1052 pCir->chip.lg->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1054 pCir->chip.lg->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1056 pCir->chip.lg->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
2174 tmp = hwp->readSeq(hwp, 0x0E);
2233 sr01 |= hwp->readSeq(hwp, 0x01) & ~0x20;
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/vgahw/
H A DvgaHW.c345 hwp->readSeq = stdReadSeq;
552 hwp->readSeq = mmioReadSeq;
586 tmp = hwp->readSeq(hwp, 0x01);
597 tmp = hwp->readSeq(hwp, 0x01);
621 scrn = hwp->readSeq(hwp, 0x01);
704 seq1 |= hwp->readSeq(hwp, 0x01) & ~0x20;
759 seq2 = hwp->readSeq(hwp, 0x02);
760 seq4 = hwp->readSeq(hwp, 0x04);
941 seq2 = hwp->readSeq(hwp, 0x02);
942 seq4 = hwp->readSeq(hw
[all...]
H A DvgaHW.h142 vgaHWReadIndexProcPtr readSeq; member in struct:_vgaHWRec
/xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/
H A DvgaHW.c343 hwp->readSeq = stdReadSeq;
551 hwp->readSeq = mmioReadSeq;
585 tmp = hwp->readSeq(hwp, 0x01);
597 tmp = hwp->readSeq(hwp, 0x01);
623 scrn = hwp->readSeq(hwp, 0x01);
709 seq1 |= hwp->readSeq(hwp, 0x01) & ~0x20;
762 seq2 = hwp->readSeq(hwp, 0x02);
763 seq4 = hwp->readSeq(hwp, 0x04);
941 seq2 = hwp->readSeq(hwp, 0x02);
942 seq4 = hwp->readSeq(hw
[all...]
H A DvgaHW.h140 vgaHWReadIndexProcPtr readSeq; member in struct:_vgaHWRec
/xsrc/external/mit/xf86-video-neomagic/dist/src/
H A Dneo.h296 #define VGArSR(index) (*hwp->readSeq)(hwp, index)
/xsrc/external/mit/xf86-video-savage/dist/src/
H A Dsavage_cursor.c57 #define inSRReg(reg) (VGAHWPTR(pScrn))->readSeq( VGAHWPTR(pScrn), reg )
H A Dsavage_driver.c998 panelX = (hwp->readSeq(hwp, 0x61) +
999 ((hwp->readSeq(hwp, 0x66) & 0x02) << 7) + 1) * 8;
1000 panelY = hwp->readSeq(hwp, 0x69) +
1001 ((hwp->readSeq(hwp, 0x6e) & 0x70) << 4) + 1;
1014 if( (hwp->readSeq( hwp, 0x39 ) & 0x03) == 0 )
1018 else if( (hwp->readSeq( hwp, 0x30 ) & 0x01) == 0 )
/xsrc/external/mit/xf86-video-tseng/dist/src/
H A Dtseng_driver.c541 oldSEQ2 = hwp->readSeq(hwp, 0x02);
542 oldSEQ4 = hwp->readSeq(hwp, 0x04);
788 pTseng->save_divide = hwp->readSeq(hwp, 0x07) & 0x40;
1594 scrn = hwp->readSeq(hwp, 0x01);
H A Dtseng_mode.c1088 tsengReg->SR06 = hwp->readSeq(hwp, 0x06);
1089 tsengReg->SR07 = hwp->readSeq(hwp, 0x07) | 0x14;
1580 seq1 |= hwp->readSeq(hwp, 0x01) & ~0x20;
1732 seq1 |= hwp->readSeq(hwp, 0x01) & ~0x20;
/xsrc/external/mit/xf86-video-nv/dist/src/
H A Driva_setup.c212 pVga->readSeq = RivaReadSeq;
H A Dnv_setup.c391 pVga->readSeq = NVReadSeq;
/xsrc/external/mit/xf86-video-chips/dist/src/
H A Dct_regs.c502 hwp->readSeq = chipsMmioReadSeq;

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