Searched refs:reads (Results 1 - 25 of 45) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dzink_bo.h97 struct zink_batch_usage *reads; member in struct:zink_bo
207 return zink_batch_usage_is_unflushed(bo->reads) ||
214 return zink_batch_usage_exists(bo->reads) ||
221 return zink_batch_usage_matches(bo->reads, bs) ||
228 if (access & ZINK_RESOURCE_ACCESS_READ && !zink_screen_usage_check_completion(screen, bo->reads))
239 zink_batch_usage_wait(ctx, bo->reads);
250 zink_batch_usage_set(&bo->reads, bs);
256 zink_batch_usage_unset(&bo->reads, bs);
258 return bo->reads || bo->writes;
H A Dzink_bo.c144 return zink_screen_usage_check_completion(screen, bo->reads) && zink_screen_usage_check_completion(screen, bo->writes);
214 bo->reads = NULL;
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_lower_memory_model.c35 bool *reads, bool *writes)
41 *reads = true;
61 *reads = true;
66 *reads = true;
87 *reads = true;
92 *reads = true;
113 *reads = true;
118 *reads = true;
139 *reads = true;
169 bool reads local in function:visit_instr
34 get_intrinsic_info(nir_intrinsic_instr * intrin,nir_variable_mode * modes,bool * reads,bool * writes) argument
[all...]
H A Dnir_lower_subgroups.c115 nir_ssa_def *reads[NIR_MAX_VEC_COMPONENTS]; local in function:lower_subgroup_op_to_scalar
136 reads[i] = lower_subgroup_op_to_32bit(b, chan_intrin);
139 reads[i] = &chan_intrin->dest.ssa;
143 return nir_vec(b, reads, intrin->num_components);
/xsrc/external/mit/freetype/dist/src/base/
H A Dftstream.c499 FT_Byte reads[2]; local in function:FT_Stream_ReadUShort
512 if ( stream->read( stream, stream->pos, reads, 2L ) != 2L )
515 p = reads;
544 FT_Byte reads[2]; local in function:FT_Stream_ReadUShortLE
557 if ( stream->read( stream, stream->pos, reads, 2L ) != 2L )
560 p = reads;
589 FT_Byte reads[3]; local in function:FT_Stream_ReadUOffset
602 if (stream->read( stream, stream->pos, reads, 3L ) != 3L )
605 p = reads;
634 FT_Byte reads[ local in function:FT_Stream_ReadULong
679 FT_Byte reads[4]; local in function:FT_Stream_ReadULongLE
[all...]
/xsrc/external/mit/mesa-demos/dist/src/tests/
H A Dpbo.c129 GLint reads = 0; local in function:Display
137 reads++;
141 pixelsPerSecond = reads * ImgWidth * ImgHeight / seconds;
142 printf("Result: %d reads in %f seconds = %f pixels/sec\n",
143 reads, seconds, pixelsPerSecond);
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.h170 #define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \
171 intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0)
173 #define OUT_RELOC_PIXMAP_FENCED(pixmap, reads, write, delta) \
174 intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 1)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_batchbuffer.h170 #define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \
171 intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0)
173 #define OUT_RELOC_PIXMAP_FENCED(pixmap, reads, write, delta) \
174 intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 1)
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_batchbuffer.h122 #define OUT_RELOC_PIXMAP(pPixmap, reads, write, delta) \
123 intel_batch_emit_reloc_pixmap(pI830, pPixmap, reads, write, delta)
/xsrc/external/mit/mesa-demos/dist/src/demos/
H A Dreadpix.c219 GLint reads = 0; local in function:Display
227 reads++;
231 mpixels = reads * (ImgWidth * ImgHeight / (1000.0 * 1000.0));
233 printf("Result: %d reads in %f seconds = %f Mpixels/sec\n",
234 reads, seconds, mpixelsPerSecond);
/xsrc/external/mit/MesaLib/dist/src/freedreno/afuc/
H A DREADME.rst50 - ``$00`` - always reads zero, otherwise seems to be the PC
124 Since ``$00`` always reads back zero, it can be used to construct
246 race with each other. It seems to be primarily used for small reads.
251 The address register increments with successive reads or writes.
277 used by ME for streaming reads (larger amounts of data). The DMA access
/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir_lower_subgroups.c123 nir_ssa_def *reads[4]; local in function:lower_subgroup_op_to_scalar
144 reads[i] = lower_subgroup_op_to_32bit(b, chan_intrin);
147 reads[i] = &chan_intrin->dest.ssa;
151 return nir_vec(b, reads, intrin->num_components);
/xsrc/external/mit/xdm/dist/xdm/
H A Dxdmcp.c389 FD_TYPE reads; local in function:WaitForSomething
394 reads = WellKnownSocketsMask;
395 nready = select (WellKnownSocketsMax + 1, &reads, NULL, NULL, NULL);
400 if (chooserFd >= 0 && FD_ISSET (chooserFd, &reads))
403 FD_CLR(chooserFd, &reads);
406 if (chooserFd6 >= 0 && FD_ISSET (chooserFd6, &reads))
409 FD_CLR(chooserFd6, &reads);
412 ProcessListenSockets(&reads);
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D9.2.3.rst60 - i965: CS writes/reads should use I915_GEM_INSTRUCTION
H A D10.0.2.rst91 - i915: Add support for gl_FragData[0] reads.
H A D11.1.1.rst161 - nvc0: free memory allocated by the prog which reads MP perf counters
163 - nv50: free memory allocated by the prog which reads MP perf counters
H A D18.1.6.rst129 - intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.
H A D18.1.8.rst117 - i965/vec4: Clamp indirect tes input array reads with 0x0fffffff
H A D20.1.9.rst62 - nir/lower_io: Eliminate oob writes and return zero for oob reads
/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/
H A Dbi_schedule.c56 /* Register reads, expressed as (equivalence classes of)
57 * sources. Only 3 reads are allowed, but up to 2 may spill as
60 bi_index reads[5]; member in struct:bi_reg_state
88 * FAU, or zero if none is assigned. Ordinarily FAU slot 0 reads zero,
694 /* Staging register reads may happen before the succeeding register
834 * whether the specified source reads from the register file via a read slot
847 /* Staging register reads bypass the usual register file mechanism */
853 if (bi_is_word_equiv(src, reg->reads[t]))
864 /* Given two tuples in source order, count the number of register reads of the
873 unsigned reads local in function:bi_count_succ_reads
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME-ISA.md213 VMEM/FLAT/GLOBAL/SCRATCH/DS instruction reads an SGPR (or EXEC, or M0).
222 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.
262 Any non-VALU instruction reads the EXEC mask. Then, any VALU instruction writes the EXEC mask.
H A DREADME.md50 Each instruction can have operands (temporaries that it reads), and definitions (temporaries that it writes).
145 HW PS reads its inputs from a special buffer that only HW VS can write to, using export instructions.
147 So in order for HW PS to be able to read the GS outputs, we must run something on the VS stage which reads the GS outputs
173 * HS, ES, GS outputs are stored in VRAM, next stage reads these from VRAM
/xsrc/external/mit/brotli/dist/c/tools/
H A Dbrotli.md40 is "`-`", `brotli` reads from standard input. All arguments after "`--`" are
/xsrc/external/mit/MesaLib/dist/docs/isl/
H A Daux-surf-comp.rst34 run a special pipeline that reads the auxiliary data and applies it to the main
H A Dunits.rst33 hardware units, everyone who ever reads :cpp:expr:`brw_mipmap_tree::qpitch` has

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