Searched refs:reg (Results 1 - 25 of 996) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h76 #define radeon_set_config_reg_seq(reg, num) do { \
77 SI_CHECK_SHADOWED_REGS(reg, num); \
78 assert((reg) < SI_CONTEXT_REG_OFFSET); \
80 radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
83 #define radeon_set_config_reg(reg, value) do { \
84 radeon_set_config_reg_seq(reg, 1); \
88 #define radeon_set_context_reg_seq(reg, num) do { \
89 SI_CHECK_SHADOWED_REGS(reg, num); \
90 assert((reg) >= SI_CONTEXT_REG_OFFSET); \
92 radeon_emit(((reg)
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
37 assert(reg < SI_CONTEXT_REG_OFFSET);
40 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
43 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) argument
45 radeon_set_config_reg_seq(cs, reg, 1);
49 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
51 assert(reg >= SI_CONTEXT_REG_OFFSET);
54 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
57 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) argument
59 radeon_set_context_reg_seq(cs, reg,
63 radeon_set_context_reg_idx(struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
74 radeon_set_sh_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
82 radeon_set_sh_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
88 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
96 radeon_set_uconfig_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
102 radeon_set_uconfig_reg_idx(struct radeon_cmdbuf * cs,struct si_screen * screen,unsigned reg,unsigned idx,unsigned value) argument
120 radeon_opt_set_context_reg(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value) argument
140 radeon_opt_set_context_reg2(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value1,unsigned value2) argument
162 radeon_opt_set_context_reg3(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value1,unsigned value2,unsigned value3) argument
187 radeon_opt_set_context_reg4(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value1,unsigned value2,unsigned value3,unsigned value4) argument
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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_live_variables.h85 * register reg.
88 var_from_reg(const simple_allocator &alloc, const src_reg &reg, argument
91 assert(reg.file == VGRF && reg.nr < alloc.count && c < 4);
92 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
94 8 * alloc.offsets[reg.nr] + reg.offset / 4 +
95 (BRW_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize;
97 assert(result < 8 * (alloc.offsets[reg.nr] + alloc.sizes[reg
102 var_from_reg(const simple_allocator & alloc,const dst_reg & reg,unsigned c=0,unsigned k=0) argument
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H A Dbrw_ir_fs.h39 fs_reg(struct ::brw_reg reg);
58 negate(fs_reg reg) argument
60 assert(reg.file != IMM);
61 reg.negate = !reg.negate;
62 return reg;
66 retype(fs_reg reg, enum brw_reg_type type) argument
68 reg.type = type;
69 return reg;
73 byte_offset(fs_reg reg, unsigne argument
104 horiz_offset(const fs_reg & reg,unsigned delta) argument
132 offset(fs_reg reg,unsigned width,unsigned delta) argument
155 component(fs_reg reg,unsigned idx) argument
248 is_periodic(const fs_reg & reg,unsigned n) argument
272 is_uniform(const fs_reg & reg) argument
282 half(const fs_reg & reg,unsigned idx) argument
293 subscript(fs_reg reg,brw_reg_type type,unsigned i) argument
317 horiz_stride(fs_reg reg,unsigned s) argument
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H A Dbrw_clip_line.c45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
48 c->reg.fixed_planes = brw_vec4_grf(i, 0);
60 c->reg.vertex[j] = brw_vec4_grf(i, 0);
64 c->reg.t = brw_vec1_grf(i, 0);
65 c->reg.t0 = brw_vec1_grf(i, 1);
66 c->reg.t1 = brw_vec1_grf(i, 2);
67 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
68 c->reg.plane_equation = brw_vec4_grf(i, 4);
71 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
72 c->reg
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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_live_variables.h111 * register reg.
114 var_from_reg(const simple_allocator &alloc, const src_reg &reg, argument
117 assert(reg.file == VGRF && reg.nr < alloc.count && c < 4);
118 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
120 8 * alloc.offsets[reg.nr] + reg.offset / 4 +
121 (BRW_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize;
123 assert(result < 8 * (alloc.offsets[reg.nr] + alloc.sizes[reg
128 var_from_reg(const simple_allocator & alloc,const dst_reg & reg,unsigned c=0,unsigned k=0) argument
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H A Dbrw_clip_line.c45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
48 c->reg.fixed_planes = brw_vec4_grf(i, 0);
60 c->reg.vertex[j] = brw_vec4_grf(i, 0);
64 c->reg.t = brw_vec1_grf(i, 0);
65 c->reg.t0 = brw_vec1_grf(i, 1);
66 c->reg.t1 = brw_vec1_grf(i, 2);
67 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
68 c->reg.plane_equation = brw_vec4_grf(i, 4);
71 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
72 c->reg
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/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v_i2c.c70 unsigned int reg = 0x10; local in function:s3v_I2CPutBits
72 if(clock) reg |= 0x1;
73 if(data) reg |= 0x2;
75 OUTREG(DDC_REG,reg);
83 unsigned int reg; local in function:s3v_I2CGetBits
85 reg = (INREG(DDC_REG));
87 *clock = reg & 0x4;
88 *data = reg & 0x8;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_swizzle.h48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
54 void (*Split)(struct rc_src_register reg, unsigned int mask, struct rc_swizzle_split * split);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a2xx/
H A Dir2_ra.c57 struct ir2_reg *reg; local in function:set_need_emit
72 reg = get_reg_src(ctx, src);
74 if (!instr->is_ssa && instr->reg == reg)
103 struct ir2_reg *reg; local in function:ra_count_refs
125 reg = get_reg_src(ctx, src);
127 reg->comp[swiz_get(src->swizzle, i)].ref_count++;
132 void ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx, argument
138 reg->comp[i].c = i;
150 for (int i = 0; i < reg
190 struct ir2_reg *reg; local in function:ra_src_free
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_screen.h42 unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx); local in function:emit_marker5
43 OUT_PKT4(ring, reg, 1);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a2xx/
H A Dir2_ra.c59 struct ir2_reg *reg; local in function:set_need_emit
74 reg = get_reg_src(ctx, src);
76 if (!instr->is_ssa && instr->reg == reg)
110 struct ir2_reg *reg; local in function:ra_count_refs
132 reg = get_reg_src(ctx, src);
134 reg->comp[swiz_get(src->swizzle, i)].ref_count++;
140 ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx, bool export, argument
146 reg->comp[i].c = i;
158 for (int i = 0; i < reg
199 struct ir2_reg *reg; local in function:ra_src_free
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_swizzle.h48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
54 void (*Split)(struct rc_src_register reg, unsigned int mask, struct rc_swizzle_split * split);
/xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/
H A Dreg_dumper.h70 #define INREG8(reg) (*(volatile uint8_t *)((pI830)->mmio + (reg)))
71 #define INREG16(reg) (*(volatile uint16_t *)((pI830)->mmio + (reg)))
72 #define INREG(reg) (*(volatile uint32_t *)((pI830)->mmio + (reg)))
73 #define OUTREG8(reg, val) \
74 *(volatile uint8_t *)((pI830)->mmio + (reg)) = (val)
75 #define OUTREG16(reg, val) \
76 *(volatile uint16_t *)((pI830)->mmio + (reg))
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) argument
55 radeon_set_config_reg_seq(cs, reg, 1);
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
62 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
66 radeon_emit(cs, (reg
70 radeon_set_context_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
77 radeon_set_context_reg_idx(struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf * cs,unsigned reg,unsigned value,unsigned mask) argument
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
108 radeon_set_sh_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
115 radeon_set_sh_reg_idx(const struct radv_physical_device * pdevice,struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
132 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
142 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
152 radeon_set_uconfig_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
159 radeon_set_uconfig_reg_idx(const struct radv_physical_device * pdevice,struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
177 radeon_set_privileged_config_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi_private.cpp54 st_src_reg *reg = ralloc(input, st_src_reg); local in function:dup_reladdr
55 if (!reg) {
60 *reg = *input;
61 return reg;
141 st_src_reg::st_src_reg(const st_src_reg &reg) argument
143 *this = reg;
146 void st_src_reg::operator=(const st_src_reg &reg) argument
148 this->type = reg.type;
149 this->file = reg.file;
150 this->index = reg
163 st_src_reg(st_dst_reg reg) argument
182 st_src_reg reg = *this; local in function:st_src_reg::get_abs
226 operator <<(std::ostream & os,const st_src_reg & reg) argument
262 st_dst_reg(st_src_reg reg) argument
316 st_dst_reg(const st_dst_reg & reg) argument
321 operator =(const st_dst_reg & reg) argument
366 operator <<(std::ostream & os,const st_dst_reg & reg) argument
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/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi_private.cpp54 st_src_reg *reg = ralloc(input, st_src_reg); local in function:dup_reladdr
55 if (!reg) {
60 *reg = *input;
61 return reg;
141 st_src_reg::st_src_reg(const st_src_reg &reg) argument
143 *this = reg;
146 void st_src_reg::operator=(const st_src_reg &reg) argument
148 this->type = reg.type;
149 this->file = reg.file;
150 this->index = reg
163 st_src_reg(st_dst_reg reg) argument
182 st_src_reg reg = *this; local in function:st_src_reg::get_abs
226 operator <<(std::ostream & os,const st_src_reg & reg) argument
262 st_dst_reg(st_src_reg reg) argument
316 st_dst_reg(const st_dst_reg & reg) argument
321 operator =(const st_dst_reg & reg) argument
366 operator <<(std::ostream & os,const st_dst_reg & reg) argument
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
44 assert(reg < SI_CONTEXT_REG_OFFSET);
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) argument
53 radeon_set_config_reg_seq(cs, reg, 1);
57 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) argument
59 assert(reg >= SI_CONTEXT_REG_OFFSET);
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
66 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) argument
68 radeon_set_context_reg_seq(cs, reg,
73 radeon_set_context_reg_idx(struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
84 radeon_set_sh_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
93 radeon_set_sh_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
99 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num) argument
108 radeon_set_uconfig_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value) argument
114 radeon_set_uconfig_reg_idx(struct radeon_cmdbuf * cs,unsigned reg,unsigned idx,unsigned value) argument
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/xsrc/external/mit/xorg-server.old/dist/hw/netbsd/x68k/
H A Dx68kText.c52 r21 = pPriv->reg->crtc.r21;
53 pPriv->reg->crtc.r21 = 0x01f0;
56 pPriv->reg->crtc.r10 = pPriv->reg->crtc.r11 = 0;
58 tpal0 = pPriv->reg->tpal[0];
59 tpal15 = pPriv->reg->tpal[15];
61 pPriv->reg->tpal[0] = 0;
62 pPriv->reg->tpal[15] = 0xFFFE;
77 pPriv->reg->crtc.r21 = r21; /* recover TVRAM mode */
78 pPriv->reg
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/xsrc/external/mit/xorg-server/dist/hw/netbsd/x68k/
H A Dx68kText.c53 r21 = pPriv->reg->crtc.r21;
54 pPriv->reg->crtc.r21 = 0x01f0;
57 pPriv->reg->crtc.r10 = pPriv->reg->crtc.r11 = 0;
59 tpal0 = pPriv->reg->tpal[0];
60 tpal15 = pPriv->reg->tpal[15];
62 pPriv->reg->tpal[0] = 0;
63 pPriv->reg->tpal[15] = 0xFFFE;
78 pPriv->reg->crtc.r21 = r21; /* recover TVRAM mode */
79 pPriv->reg
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/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_program.h237 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
240 #define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)
241 #define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)
245 #define A0_DEST(reg) (((reg) & UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
246 #define D0_DEST(reg) (((reg)
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/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_program.h237 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
240 #define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)
241 #define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)
245 #define A0_DEST(reg) (((reg) & UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
246 #define D0_DEST(reg) (((reg)
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/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_program.h238 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
241 #define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)
242 #define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)
246 #define A0_DEST(reg) (((reg) & UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
247 #define D0_DEST(reg) (((reg)
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/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/test/
H A Dtest-constant-fold.c65 bi_index reg = bi_register(0); local in function:main
68 CASE(bi_swz_v2i16_to(b, reg, bi_imm_u32(0xCAFEBABE)), 0xCAFEBABE);
69 CASE(bi_swz_v2i16_to(b, reg, bi_swz_16(bi_imm_u32(0xCAFEBABE), false, false)),
71 CASE(bi_swz_v2i16_to(b, reg, bi_swz_16(bi_imm_u32(0xCAFEBABE), true, false)),
73 CASE(bi_swz_v2i16_to(b, reg, bi_swz_16(bi_imm_u32(0xCAFEBABE), true, true)),
77 CASE(bi_mkvec_v2i16_to(b, reg, bi_imm_u16(0xCAFE), bi_imm_u16(0xBABE)), 0xBABECAFE);
78 CASE(bi_mkvec_v2i16_to(b, reg, bi_swz_16(bi_imm_u32(0xCAFEBABE), true, true),
80 CASE(bi_mkvec_v2i16_to(b, reg, bi_swz_16(bi_imm_u32(0xCAFEBABE), true, true),
89 CASE(bi_mkvec_v4i8_to(b, reg, a, a, a, a), 0xBEBEBEBE);
90 CASE(bi_mkvec_v4i8_to(b, reg,
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/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_lower_regs_to_ssa.c48 nir_register *reg = src->reg.reg; local in function:rewrite_src
49 struct nir_phi_builder_value *value = state->values[reg->index];
74 nir_register *reg = nif->condition.reg.reg; local in function:rewrite_if_condition
75 struct nir_phi_builder_value *value = state->values[reg->index];
91 nir_instr *instr = dest->reg.parent_instr;
92 nir_register *reg local in function:rewrite_dest
114 nir_register *reg = alu->dest.dest.reg.reg; local in function:rewrite_alu_instr
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