| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_reindex_ssa.cpp | 44 RegClass rc = def.regClass();
58 assert(op.regClass() == ctx.temp_rc[new_id]);
59 op.setTemp(Temp(new_id, op.regClass()));
91 program->private_segment_buffer.regClass());
93 Temp(ctx.renames[program->scratch_offset.id()], program->scratch_offset.regClass());
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| H A D | aco_validate.cpp | 232 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
235 if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
242 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed())
246 check(instr->definitions[0].regClass() == v1, "VOP3P must have v1 definition",
268 if (instr->definitions[i].regClass().is_subdword())
327 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
330 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
337 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr),
339 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
347 check(i != 2 || (op.isTemp() && op.regClass()
[all...] |
| H A D | aco_lower_to_hw_instr.cpp | 193 assert(instr->definitions[1].regClass() == bld.lm);
513 if (src.regClass() == v1b) {
534 } else if (src.regClass() == v2b) {
814 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) {
827 if (dst.regClass().type() == RegType::sgpr) {
861 assert(dst.regClass() == v1);
862 assert(tmp_exec.regClass() == bld.lm);
864 assert(same_half.regClass() == bld.lm);
865 assert(index_x4.regClass() == v1);
866 assert(input_data.regClass()
[all...] |
| H A D | aco_instruction_selection.cpp | 151 RegClass rc = RegClass(mask.regClass().type(), 1);
173 dst = bld.tmp(src.regClass());
193 if (index.regClass() == s1)
341 if (src.regClass() == dst_rc) {
349 if (it != ctx->allocated_vec.end() && dst_rc.bytes() == it->second[idx].regClass().bytes()) {
350 if (it->second[idx].regClass() == dst_rc) {
527 if (vec.regClass() == dst.regClass()) {
572 assert(val.regClass() == s1);
573 assert(dst.regClass()
[all...] |
| H A D | aco_lower_to_cssa.cpp | 103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) {
118 Temp tmp = bld.tmp(def.regClass());
173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom
359 if (copy.op.regClass() != copy.def.regClass())
393 if (cp.def.regClass().type() != type || it->second.num_uses > 0) {
413 [&](auto& n) { return n.second.cp.def.regClass().type() == type; });
424 while (it->second.cp.def.regClass().type() != type)
466 bool is_vgpr = cp.def.regClass()
[all...] |
| H A D | aco_register_allocation.cpp | 59 rc = def.regClass();
304 if (op.regClass().is_subdword())
310 void clear(Operand op) { clear(op.physReg(), op.regClass()); }
314 if (def.regClass().is_subdword())
320 void clear(Definition def) { clear(def.physReg(), def.regClass()); }
783 copy.second.setTemp(ctx.program->allocateTmp(copy.second.regClass()));
784 ctx.assignments.emplace_back(copy.second.physReg(), copy.second.regClass());
1049 Definition pc_def = Definition(res.first, pc_op.regClass());
1138 Definition pc_def = Definition(reg_win.lo(), pc_op.regClass());
1495 if (get_reg_specified(ctx, reg_file, temp.regClass(), inst
[all...] |
| H A D | aco_lower_phis.cpp | 318 if (phi->operands[i].regClass() == phi->definitions[0].regClass())
325 assert(phi_src.regClass().type() == RegType::sgpr);
328 Temp new_phi_src = bld.tmp(phi->definitions[0].regClass());
347 assert(program->wave_size == 64 ? phi->definitions[0].regClass() != s1
348 : phi->definitions[0].regClass() != s2);
349 if (phi->definitions[0].regClass() == program->lane_mask)
351 else if (phi->definitions[0].regClass().is_subdword())
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| H A D | aco_opt_value_numbering.cpp | 150 if (a->definitions[i].regClass() != b->definitions[i].regClass())
385 instr->operands[0].regClass() == instr->definitions[0].regClass()) {
401 assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass());
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| H A D | aco_optimizer_postRA.cpp | 91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255);
92 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256);
98 if (def.regClass().is_subdword())
102 assert(def.size() == dw_size || def.regClass().is_subdword());
135 instr_idx = last_writer_idx(ctx, op.physReg(), op.regClass());
177 return is_clobbered_since(ctx, t.physReg(), t.regClass(), idx);
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| H A D | aco_reduce_assign.cpp | 102 reduceTmp = program->allocateTmp(reduceTmp.regClass());
144 vtmp = program->allocateTmp(vtmp.regClass());
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| H A D | aco_spill.cpp | 200 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear())
410 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear())
556 spill_id = ctx.allocate_spill_id(to_spill.regClass());
587 ctx.spills_entry[block_idx][to_spill] = ctx.allocate_spill_id(to_spill.regClass());
716 ctx.allocate_spill_id(phi->definitions[0].regClass());
744 ctx.spills_entry[block_idx][to_spill] = ctx.allocate_spill_id(to_spill.regClass());
790 Temp new_name = ctx.program->allocateTmp(live.first.regClass());
825 Temp new_name = ctx.program->allocateTmp(live.first.regClass());
[all...] |
| H A D | aco_optimizer.cpp | 510 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; });
519 [](const Definition& def) { return def.regClass().is_subdword(); });
553 if (temp.regClass() == instr->definitions[0].regClass())
672 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
986 instr->operands[i] = Operand(instr->operands[i].regClass());
988 while (info.is_temp() && info.temp.regClass() == instr->operands[i].getTemp().regClass()) {
1123 base.regClass() == v1 && mubuf.offset + offset < 4096) {
1131 base.regClass()
[all...] |
| H A D | aco_ir.h | 411 constexpr RegClass regClass() const noexcept { return (RegClass::RC)reg_class; } function in struct:aco::Temp
413 constexpr unsigned bytes() const noexcept { return regClass().bytes(); }
414 constexpr unsigned size() const noexcept { return regClass().size(); }
415 constexpr RegType type() const noexcept { return regClass().type(); }
416 constexpr bool is_linear() const noexcept { return regClass().is_linear(); }
730 constexpr RegClass regClass() const noexcept { return data_.temp.regClass(); } function in class:aco::Operand
799 return hasRegClass() && regClass().type() == type;
846 return other.isUndefined() && other.regClass() == regClass();
917 constexpr RegClass regClass() const noexcept { return temp.regClass(); } function in class:aco::Definition
[all...] |
| H A D | aco_insert_NOPs.cpp | 412 if (def.regClass().type() != RegType::sgpr) {
443 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr)
504 if (def.regClass().type() == RegType::sgpr) {
542 instr->operands[1].regClass().type() == RegType::vgpr &&
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| H A D | aco_insert_waitcnt.cpp | 274 instr->operands[1].regClass() == s4;
599 insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false, has_sampler);
605 insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true, has_sampler);
682 instr->operands[1].regClass() == s4;
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| H A D | aco_print_ir.cpp | 169 print_reg_class(operand->regClass(), output);
193 print_reg_class(definition->regClass(), output);
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| H A D | aco_insert_exec_mask.cpp | 342 return Operand(exec, t.regClass());
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 1197 - aco: refactor regClass setup for subdword VGPRs
|