Searched refs:reg_base (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/gp/
H A Dregalloc.c402 for (unsigned reg_base = 0; local in function:find_free_value_reg
403 reg_base < GPIR_PHYSICAL_REG_NUM + GPIR_VALUE_REG_NUM;
404 reg_base++) {
405 unsigned cur_reg = (reg_base + reg_offset) % (GPIR_PHYSICAL_REG_NUM + GPIR_VALUE_REG_NUM);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/
H A Dnir.c107 child = comp->var_nodes[(reg->index << 2) + comp->reg_base + swizzle];
448 comp->reg_base = num_ssa;
H A Dnode.c310 comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
H A Dppir.h315 unsigned reg_base; member in struct:ppir_compiler
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_perfcounter.c640 unsigned reg_base = regs->select0; local in function:si_pc_emit_select
645 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
655 reg_base -= (reg_count - 1) * 4;
656 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/pp/
H A Dnir.c109 child = comp->var_nodes[(reg->index << 2) + comp->reg_base + swizzle];
114 comp->var_nodes[(reg->index << 2) + comp->reg_base + swizzle] = child;
785 comp->reg_base = num_ssa;
H A Dnode.c369 comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
H A Dppir.h371 unsigned reg_base; member in struct:ppir_compiler

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