Searched refs:reg_index (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A Dparse_kernel_headers.py775 reg_index = type_map.index(name) if name in type_map else -1
776 if reg_index >= 1 and reg_index % 2 == 1:
777 type_name = type_map[reg_index - 1]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_shader_tgsi_setup.c200 unsigned reg_index,
213 if (reg_index >= array->range.First && reg_index <= array->range.Last)
222 unsigned File, unsigned reg_index,
229 unsigned array_id = get_temp_array_id(bld_base, reg_index, reg);
250 unsigned reg_index,
262 array_id = get_temp_array_id(&ctx->bld_base, reg_index, reg_indirect);
276 reg_index - ctx->temp_arrays[array_id - 1].range.First);
347 unsigned reg_index,
354 ptr = get_pointer_into_array(ctx, file, swizzle, reg_index, reg_indirec
199 get_temp_array_id(struct lp_build_tgsi_context * bld_base,unsigned reg_index,const struct tgsi_ind_register * reg) argument
221 get_array_range(struct lp_build_tgsi_context * bld_base,unsigned File,unsigned reg_index,const struct tgsi_ind_register * reg) argument
247 get_pointer_into_array(struct si_shader_context * ctx,unsigned file,unsigned swizzle,unsigned reg_index,const struct tgsi_ind_register * reg_indirect) argument
343 load_value_from_array(struct lp_build_tgsi_context * bld_base,unsigned file,enum tgsi_opcode_type type,unsigned swizzle,unsigned reg_index,const struct tgsi_ind_register * reg_indirect) argument
378 store_value_to_array(struct lp_build_tgsi_context * bld_base,LLVMValueRef value,unsigned file,unsigned chan_index,unsigned reg_index,const struct tgsi_ind_register * reg_indirect) argument
810 unsigned reg_index = reg->Register.Index; local in function:si_llvm_emit_store
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H A Dsi_shader.c2627 unsigned reg_index; local in function:si_llvm_emit_clipvertex
2636 for (reg_index = 0; reg_index < 2; reg_index ++) {
2637 struct ac_export_args *args = &pos[2 + reg_index];
2648 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2660 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/
H A Dregalloc.c127 int reg_index = 0; local in function:ppir_regalloc_init
129 while (reg_index < ppir_ra_reg_base[i + 1])
130 ra_class_add_reg(ret, i, reg_index++);
723 int reg_index = ra_get_node_reg(g, n++); local in function:ppir_regalloc_prog_try
724 reg->index = get_phy_reg_index(reg_index);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_shader_llvm_vs.c395 unsigned reg_index; local in function:si_llvm_emit_clipvertex
405 for (reg_index = 0; reg_index < 2; reg_index++) {
406 struct ac_export_args *args = &pos[2 + reg_index];
408 if (!(clipdist_mask & BITFIELD_RANGE(reg_index * 4, 4)))
415 if (!(clipdist_mask & BITFIELD_BIT(reg_index * 4 + chan)))
420 LLVMConstInt(ctx->ac.i32, ((reg_index * 4 + chan) * 4 + const_chan) * 4, 0);
431 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/
H A Dr300_reg.h2947 #define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, saturate) \
2951 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/
H A Dr300_reg.h2947 #define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, saturate) \
2951 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c3496 unsigned reg_index = emit->clip_dist_out_index + i / 4; local in function:emit_clip_distance_from_vpos
3501 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3538 unsigned reg_index = emit->clip_dist_out_index + i / 4; local in function:emit_clip_vertex_instructions
3543 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_register_allocation.cpp843 auto is_free = [&](PhysReg reg_index)
844 { return reg_file[reg_index] == 0 && !ctx.war_hint[reg_index]; };
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c1062 unsigned reg_file, unsigned reg_index,
1077 base = lp_build_const_int_vec(bld->bld_base.base.gallivm, uint_bld->type, reg_index);
1061 get_indirect_index(struct lp_build_tgsi_soa_context * bld,unsigned reg_file,unsigned reg_index,const struct tgsi_ind_register * indirect_reg,int index_limit) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c6185 unsigned reg_index = emit->clip_dist_out_index + i / 4; local in function:emit_clip_distance_from_vpos
6190 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
6228 unsigned reg_index = emit->clip_dist_out_index + i / 4; local in function:emit_clip_vertex_instructions
6233 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c673 unsigned reg_file, unsigned reg_index,
688 base = lp_build_const_int_vec(bld->bld_base.base.gallivm, uint_bld->type, reg_index);
672 get_indirect_index(struct lp_build_tgsi_soa_context * bld,unsigned reg_file,unsigned reg_index,const struct tgsi_ind_register * indirect_reg,int index_limit) argument

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