Searched refs:regs (Results 1 - 25 of 208) sorted by relevance

123456789

/xsrc/external/mit/MesaLib.old/dist/src/mesa/x86-64/
H A Dx86-64.c44 extern void _mesa_x86_64_cpuid(unsigned int *regs);
77 unsigned int regs[4]; local in function:_mesa_init_all_x86_64_transform_asm
93 regs[0] = 0x80000001;
94 regs[1] = 0x00000000;
95 regs[2] = 0x00000000;
96 regs[3] = 0x00000000;
97 _mesa_x86_64_cpuid(regs);
98 if (regs[3] & (1U << 31)) {
/xsrc/external/mit/MesaLib/dist/src/mesa/x86-64/
H A Dx86-64.c44 extern void _mesa_x86_64_cpuid(unsigned int *regs);
77 unsigned int regs[4]; local in function:_mesa_init_all_x86_64_transform_asm
93 regs[0] = 0x80000001;
94 regs[1] = 0x00000000;
95 regs[2] = 0x00000000;
96 regs[3] = 0x00000000;
97 _mesa_x86_64_cpuid(regs);
98 if (regs[3] & (1U << 31)) {
/xsrc/external/mit/MesaLib.old/dist/src/util/
H A Dregister_allocate.c91 struct ra_reg *regs; member in struct:ra_regs
106 BITSET_WORD *regs; member in struct:ra_class
111 * This is "how many regs are in the set."
161 struct ra_regs *regs; member in struct:ra_graph
177 unsigned int (*select_reg_callback)(struct ra_graph *g, BITSET_WORD *regs,
192 struct ra_regs *regs; local in function:ra_alloc_reg_set
194 regs = rzalloc(mem_ctx, struct ra_regs);
195 regs->count = count;
196 regs->regs
229 ra_set_allocate_round_robin(struct ra_regs * regs) argument
235 ra_add_conflict_list(struct ra_regs * regs,unsigned int r1,unsigned int r2) argument
251 ra_add_reg_conflict(struct ra_regs * regs,unsigned int r1,unsigned int r2) argument
268 ra_add_transitive_reg_conflict(struct ra_regs * regs,unsigned int base_reg,unsigned int reg) argument
290 ra_make_reg_conflicts_transitive(struct ra_regs * regs,unsigned int r) argument
305 ra_alloc_reg_class(struct ra_regs * regs) argument
321 ra_class_add_reg(struct ra_regs * regs,unsigned int c,unsigned int r) argument
345 ra_set_finalize(struct ra_regs * regs,unsigned int ** q_values) argument
417 ra_alloc_interference_graph(struct ra_regs * regs,unsigned int count) argument
445 ra_set_select_reg_callback(struct ra_graph * g,unsigned int (* callback)(struct ra_graph * g,BITSET_WORD * regs,void * data),void * data) argument
578 ra_compute_available_regs(struct ra_graph * g,unsigned int n,BITSET_WORD * regs) argument
[all...]
H A Dregister_allocate.h52 void ra_set_allocate_round_robin(struct ra_regs *regs);
53 unsigned int ra_alloc_reg_class(struct ra_regs *regs);
54 void ra_add_reg_conflict(struct ra_regs *regs,
56 void ra_add_transitive_reg_conflict(struct ra_regs *regs,
58 void ra_make_reg_conflicts_transitive(struct ra_regs *regs, unsigned int reg);
59 void ra_class_add_reg(struct ra_regs *regs, unsigned int c, unsigned int reg);
60 void ra_set_num_conflicts(struct ra_regs *regs, unsigned int class_a,
62 void ra_set_finalize(struct ra_regs *regs, unsigned int **conflicts);
75 struct ra_graph *ra_alloc_interference_graph(struct ra_regs *regs,
80 BITSET_WORD *regs,
[all...]
/xsrc/external/mit/MesaLib/dist/src/util/
H A Dregister_allocate.c95 struct ra_regs *regs; local in function:ra_alloc_reg_set
97 regs = rzalloc(mem_ctx, struct ra_regs);
98 regs->count = count;
99 regs->regs = rzalloc_array(regs, struct ra_reg, count);
102 regs->regs[i].conflicts = rzalloc_array(regs->regs, BITSET_WOR
126 ra_set_allocate_round_robin(struct ra_regs * regs) argument
132 ra_add_conflict_list(struct ra_regs * regs,unsigned int r1,unsigned int r2) argument
143 ra_add_reg_conflict(struct ra_regs * regs,unsigned int r1,unsigned int r2) argument
160 ra_add_transitive_reg_conflict(struct ra_regs * regs,unsigned int base_reg,unsigned int reg) argument
179 ra_add_transitive_reg_pair_conflict(struct ra_regs * regs,unsigned int base_reg,unsigned int reg0,unsigned int reg1) argument
204 ra_make_reg_conflicts_transitive(struct ra_regs * regs,unsigned int r) argument
218 ra_alloc_reg_class(struct ra_regs * regs) argument
245 ra_alloc_contig_reg_class(struct ra_regs * regs,int contig_len) argument
256 ra_get_class_from_index(struct ra_regs * regs,unsigned int class) argument
293 ra_set_finalize(struct ra_regs * regs,unsigned int ** q_values) argument
398 ra_set_serialize(const struct ra_regs * regs,struct blob * blob) argument
434 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, reg_count, false); local in function:ra_set_deserialize
557 ra_alloc_interference_graph(struct ra_regs * regs,unsigned int count) argument
833 ra_compute_available_regs(struct ra_graph * g,unsigned int n,BITSET_WORD * regs) argument
[all...]
H A Dregister_allocate.h55 void ra_set_allocate_round_robin(struct ra_regs *regs);
56 struct ra_class *ra_alloc_reg_class(struct ra_regs *regs);
57 struct ra_class *ra_alloc_contig_reg_class(struct ra_regs *regs, int contig_len);
59 void ra_add_reg_conflict(struct ra_regs *regs,
61 void ra_add_transitive_reg_conflict(struct ra_regs *regs,
65 ra_add_transitive_reg_pair_conflict(struct ra_regs *regs,
68 void ra_make_reg_conflicts_transitive(struct ra_regs *regs, unsigned int reg);
70 struct ra_class *ra_get_class_from_index(struct ra_regs *regs, unsigned int c);
71 void ra_set_num_conflicts(struct ra_regs *regs, unsigned int class_a,
73 void ra_set_finalize(struct ra_regs *regs, unsigne
[all...]
H A Dregister_allocate_test.cpp49 thumb_checks(struct ra_regs *regs, unsigned reg32_base, unsigned reg64_base) argument
51 struct ra_class *reg32low = ra_get_class_from_index(regs, 0);
52 struct ra_class *reg64low = ra_get_class_from_index(regs, 1);
53 struct ra_class *reg96 = ra_get_class_from_index(regs, 2);
69 /* These individual regs should conflict with themselves, but nothing else from their class */
88 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 100, true); local in function:TEST_F
95 struct ra_class *reg32low = ra_alloc_reg_class(regs);
99 ra_add_transitive_reg_conflict(regs, i, vreg);
104 struct ra_class *reg64low = ra_alloc_reg_class(regs);
108 ra_add_transitive_reg_conflict(regs,
128 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 16, true); local in function:TEST_F
152 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 16, true); local in function:TEST_F
173 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, base_regs, true); local in function:TEST_F
[all...]
H A Dregister_allocate_internal.h47 struct ra_reg *regs; member in struct:ra_regs
64 BITSET_WORD *regs; member in struct:ra_class
67 * Number of regs after each bit in *regs that are also conflicted by an
75 * This is "how many regs are in the set."
130 struct ra_regs *regs; member in struct:ra_graph
/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/
H A Dbi_pack.c64 bi_assign_slot_read(bi_registers *regs, bi_index src) argument
72 if (regs->slot[i] == src.value && regs->enabled[i])
76 if (regs->slot[2] == src.value && regs->slot23.slot2 == BIFROST_OP_READ)
82 if (!regs->enabled[i]) {
83 regs->slot[i] = src.value;
84 regs->enabled[i] = true;
89 if (!regs->slot23.slot3) {
90 regs
173 bi_pack_registers(bi_registers regs) argument
265 bi_flip_slots(bi_registers * regs) argument
276 bi_get_src_slot(bi_registers * regs,unsigned reg) argument
289 bi_get_src_new(bi_instr * ins,bi_registers * regs,unsigned s) argument
[all...]
H A Dbi_print.c44 bi_print_slots(bi_registers *regs, FILE *fp) argument
47 if (regs->enabled[i])
48 fprintf(fp, "slot %u: %u\n", i, regs->slot[i]);
51 if (regs->slot23.slot2) {
53 bi_reg_op_name(regs->slot23.slot2),
54 regs->slot23.slot2 >= BIFROST_OP_WRITE ?
56 regs->slot[2]);
59 if (regs->slot23.slot3) {
61 bi_reg_op_name(regs->slot23.slot3),
62 regs
[all...]
/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Dnewmmio.h342 union { pci_conf_regs regs;
345 union { streams_proc_regs regs;
348 union { memport_proc_regs regs;
351 union { vga_3bd_regs regs;
354 union { vga_3c_regs regs;
357 union { vga_3bd_regs regs;
360 union { subsys_regs regs;
363 union { dma_regs regs;
366 union { colpatt_regs regs;
369 union { bltfill_regs regs;
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler.c41 compiler->regs = etna_ra_setup(compiler);
42 if (!compiler->regs) {
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_pack.h55 const struct fd_reg_pair regs[] = {__VA_ARGS__}; \
56 /* NOTE: allow regs[0].reg==0, this happens in OUT_PKT() */ \
57 if (i < ARRAY_SIZE(regs) && (i == 0 || regs[i].reg > 0)) { \
58 __assert_eq(regs[0].reg + i, regs[i].reg); \
59 if (regs[i].bo) { \
62 OUT_RELOC(ring, regs[i].bo, regs[i].bo_offset, regs[
[all...]
/xsrc/external/mit/xf86-video-s3/dist/src/
H A Dnewmmio.h171 union { pci_conf_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4120a
174 union { packed_enhanced_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4130a
177 union { streams_proc_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4140a
183 union { vga_3bd_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4160a
186 union { vga_3c_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4170a
189 union { vga_3bd_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4180a
192 union { subsys_regs regs; member in union:__anon6afe68d41108::__anon6afe68d4190a
195 union { enhanced_regs regs; member in union:__anon6afe68d41108::__anon6afe68d41a0a
198 union { lpbus_regs regs; member in union:__anon6afe68d41108::__anon6afe68d41b0a
209 #define SET_WRT_MASK(msk) ((mmtr)s3MmioMem)->pk_enh_regs.regs
[all...]
H A Ds3_reg.h175 * streams regs
177 #define SET_BLEND_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.blend_cntl = (val)
178 #define SET_PSTREAM_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_stream_cntl = (val)
179 #define SET_PSTREAM_FBADDR0(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_fbaddr0 = (val)
180 #define SET_PSTREAM_FBADDR1(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_fbaddr1 = (val)
181 #define SET_PSTREAM_STRIDE(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_stream_stride = (val)
182 #define SET_PSTREAM_START(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_start_coord = (val)
183 #define SET_PSTREAM_WIND(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_window_size = (val)
184 #define SET_SSTREAM_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_stream_cntl = (val)
185 #define SET_SSTRETCH(val) ((mmtr)s3MmioMem)->streams_regs.regs
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_cs.h329 #define __ONE_REG(i, regs) \
331 if (i < ARRAY_SIZE(regs) && regs[i].reg > 0) { \
332 __assert_eq(regs[0].reg + i, regs[i].reg); \
333 if (regs[i].bo) { \
334 uint64_t v = regs[i].bo->iova + regs[i].bo_offset; \
335 v >>= regs[i].bo_shift; \
336 v |= regs[
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c115 if (vc4->regs)
118 vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
125 vc4->reg_class_any[i] = ra_alloc_reg_class(vc4->regs);
126 vc4->reg_class_a_or_b[i] = ra_alloc_reg_class(vc4->regs);
127 vc4->reg_class_a_or_b_or_acc[i] = ra_alloc_reg_class(vc4->regs);
128 vc4->reg_class_r4_or_a[i] = ra_alloc_reg_class(vc4->regs);
129 vc4->reg_class_a[i] = ra_alloc_reg_class(vc4->regs);
131 vc4->reg_class_r0_r3 = ra_alloc_reg_class(vc4->regs);
135 ra_class_add_reg(vc4->regs, vc4->reg_class_r0_r3, i);
136 ra_class_add_reg(vc4->regs, vc
211 vc4_ra_select_callback(struct ra_graph * g,BITSET_WORD * regs,void * data) argument
[all...]
/xsrc/external/mit/xf86-video-tdfx/dist/src/
H A Dtdfx_dri.h8 drm_handle_t regs; member in struct:__anon437464dc0108
/xsrc/external/mit/xf86-video-ngle/dist/src/
H A Dngle.h55 void *regs; member in struct:__anon7f39eb3e0108
87 volatile uint32_t *ptr = (uint32_t *)((uint8_t *)fPtr->regs + offset);
94 volatile uint8_t *ptr = (uint8_t *)fPtr->regs + offset;
101 volatile uint32_t *ptr = (uint32_t *)((uint8_t *)fPtr->regs + offset);
108 volatile uint8_t *ptr = (uint8_t *)fPtr->regs + offset;
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_cp.c47 struct ir3_register *dst = instr->regs[0];
48 struct ir3_register *src = instr->regs[1];
103 if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
138 struct ir3_register *reg = instr->regs[m];
232 unsigned srcflags = src->regs[1]->flags;
266 struct ir3_instruction *srcsrc = ssa(src->regs[1]);
369 struct ir3_register *src_reg = src->regs[1];
393 struct ir3_register *src_reg = src->regs[1];
402 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
414 !(instr->regs[
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/decode/scripts/
H A Dtest.lua15 io.write("0x2280: written=" .. regs.written(0x2280) .. ", lastval=" .. regs.lastval(0x2280) .. ", val=" .. regs.val(0x2280) .. "\n")
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/panfrost/bifrost/
H A Ddisassemble.c63 static unsigned get_reg0(struct bifrost_regs regs) argument
65 if (regs.ctrl == 0)
66 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
68 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
71 static unsigned get_reg1(struct bifrost_regs regs) argument
73 return regs
274 DecodeRegCtrl(struct bifrost_regs regs) argument
334 GetRegToWrite(enum bifrost_reg_write_unit unit,struct bifrost_regs regs) argument
890 dump_fma(uint64_t word,struct bifrost_regs regs,struct bifrost_regs next_regs,uint64_t * consts,bool verbose) argument
1402 dump_add(uint64_t word,struct bifrost_regs regs,struct bifrost_regs next_regs,uint64_t * consts,unsigned data_reg,unsigned offset,bool verbose) argument
1983 struct bifrost_regs regs; local in function:dump_instr
[all...]
/xsrc/external/mit/MesaLib/dist/src/nouveau/drm-shim/
H A DREADME.md17 | 50 | G80 | GeForce 8800 GTS | SM 1.0, 128 regs |
21 | c0 | GF100 | GeForce GTX 480 | SM 2.0, 64 regs |
22 | e4 | GK104 | GeForce GTX 680 | SM 3.0, 64 regs |
23 | f0 | GK110 | GeForce GTX 780 | SM 3.5, 256 regs |
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_regalloc.h55 struct ra_regs *regs; member in struct:rc_regalloc_state
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_regalloc.h55 struct ra_regs *regs; member in struct:rc_regalloc_state

Completed in 21 milliseconds

123456789