Searched refs:regs_written (Results 1 - 25 of 38) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_fs_validate.cpp47 fsv_assert(inst->dst.offset / REG_SIZE + regs_written(inst) <=
H A Dbrw_fs_dead_code_eliminate.cpp94 for (unsigned i = 0; i < regs_written(inst); i++)
112 for (unsigned i = 0; i < regs_written(inst); i++) {
H A Dbrw_fs_register_coalesce.cpp197 channels_remaining -= regs_written(inst);
213 channels_remaining -= regs_written(inst);
H A Dbrw_fs_cse.cpp205 unsigned written = regs_written(inst);
241 assert(regs_written(copy) == written);
291 int written = regs_written(entry->generator);
H A Dbrw_schedule_instructions.cpp1146 for (unsigned r = 0; r < regs_written(inst); r++) {
1151 for (unsigned r = 0; r < regs_written(inst); r++) {
1173 for (unsigned r = 0; r < regs_written(inst); r++)
1274 for (unsigned r = 0; r < regs_written(inst); r++)
1277 for (unsigned r = 0; r < regs_written(inst); r++) {
1297 for (unsigned r = 0; r < regs_written(inst); r++)
1395 for (unsigned j = 0; j < regs_written(inst); ++j) {
1476 for (unsigned j = 0; j < regs_written(inst); ++j)
H A Dbrw_fs_reg_allocate.cpp892 spill_costs[inst->dst.nr] += regs_written(inst) * block_scale;
1021 fs_reg spill_src(VGRF, alloc.allocate(regs_written(inst)));
1058 * regs_written(inst), then we need to unspill the destination since
1059 * we write back out all of the regs_written(). If the original
1067 regs_written(inst));
1070 subset_spill_offset, regs_written(inst));
H A Dbrw_fs_live_variables.cpp134 for (unsigned j = 0; j < regs_written(inst); j++) {
H A Dbrw_vec4_cse.cpp210 regs_written(entry->generator)),
H A Dbrw_ir_fs.h439 regs_written(const fs_inst *inst) function in typeref:typename:unsigned
H A Dbrw_ir_vec4.h416 regs_written(const vec4_instruction *inst) function in namespace:brw
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_fs_validate.cpp47 fsv_assert(inst->dst.offset / REG_SIZE + regs_written(inst) <=
H A Dbrw_fs_dead_code_eliminate.cpp96 for (unsigned i = 0; i < regs_written(inst); i++)
115 for (unsigned i = 0; i < regs_written(inst); i++) {
H A Dbrw_fs_cse.cpp206 unsigned written = regs_written(inst);
242 assert(regs_written(copy) == written);
291 int written = regs_written(entry->generator);
H A Dbrw_fs_register_coalesce.cpp233 channels_remaining -= regs_written(inst);
249 channels_remaining -= regs_written(inst);
H A Dbrw_schedule_instructions.cpp1216 for (unsigned r = 0; r < regs_written(inst); r++) {
1221 for (unsigned r = 0; r < regs_written(inst); r++) {
1243 for (unsigned r = 0; r < regs_written(inst); r++) {
1347 for (unsigned r = 0; r < regs_written(inst); r++)
1350 for (unsigned r = 0; r < regs_written(inst); r++) {
1370 for (unsigned r = 0; r < regs_written(inst); r++)
1468 for (unsigned j = 0; j < regs_written(inst); ++j) {
1550 for (unsigned j = 0; j < regs_written(inst); ++j)
H A Dbrw_fs_reg_allocate.cpp262 for (unsigned j = 0; j < regs_written(inst); j++) {
885 spill_costs[inst->dst.nr] += regs_written(inst) * block_scale;
1111 fs_reg spill_src = alloc_spill_reg(regs_written(inst), ip);
1148 * regs_written(inst), then we need to unspill the destination since
1149 * we write back out all of the regs_written(). If the original
1157 regs_written(inst));
1160 subset_spill_offset, regs_written(inst));
H A Dbrw_fs_live_variables.cpp134 for (unsigned j = 0; j < regs_written(inst); j++) {
358 !check_register_live_range(this, ip, inst->dst, regs_written(inst)))
H A Dbrw_ir_performance.cpp1374 for (unsigned j = 0; j < regs_written(inst); j++)
1423 for (unsigned j = 0; j < regs_written(inst); j++) {
1491 for (unsigned j = 0; j < regs_written(inst); j++)
1528 for (unsigned j = 0; j < regs_written(inst); j++) {
H A Dbrw_vec4_cse.cpp210 regs_written(entry->generator)),
H A Dbrw_vec4_live_variables.cpp291 regs_written(inst)))
/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/
H A Dst_atifs_to_nir.c56 bool regs_written[MAX_NUM_PASSES_ATI][MAX_NUM_FRAGMENT_REGISTERS_ATI]; member in struct:st_translate
149 if (t->regs_written[t->current_pass][src_type - GL_REG_0_ATI]) {
337 if (t->regs_written[0][reg]) {
387 t->regs_written[t->current_pass][r] = true;
420 t->regs_written[t->current_pass][dstreg] = true;
482 if (t->regs_written[atifs->NumPasses-1][0]) {
/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/
H A Dst_atifs_to_tgsi.c53 bool regs_written[MAX_NUM_PASSES_ATI][MAX_NUM_FRAGMENT_REGISTERS_ATI]; member in struct:st_translate
129 if (t->regs_written[t->current_pass][src_type - GL_REG_0_ATI]) {
323 if (t->regs_written[0][reg]) {
341 t->regs_written[t->current_pass][r] = true;
396 t->regs_written[t->current_pass][dstreg] = true;
406 if (t->regs_written[numPasses-1][0]) {
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.2.4.rst103 - i965/fs: Set correct number of regs_written for MCS fetches.
H A D17.0.5.rst73 - intel/fs: Use regs_written() in spilling cost heuristic for improved
H A D8.0.1.rst118 - i965/fs: Add a new fs_inst::regs_written function.

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