| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_lower_to_hw_instr.cpp | 200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask,
215 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask,
220 dpp_ctrl, row_mask, bank_mask, bound_ctrl);
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl);
225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask,
227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask,
230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask,
232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask,
235 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask,
237 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mas
199 emit_int64_dpp_op(lower_context * ctx,PhysReg dst_reg,PhysReg src0_reg,PhysReg src1_reg,PhysReg vtmp_reg,ReduceOp op,unsigned dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl,Operand * identity=NULL) argument
386 emit_dpp_op(lower_context * ctx,PhysReg dst_reg,PhysReg src0_reg,PhysReg src1_reg,PhysReg vtmp,ReduceOp op,unsigned size,unsigned dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl,Operand * identity=NULL) argument
454 emit_dpp_mov(lower_context * ctx,PhysReg dst,PhysReg src0,unsigned size,unsigned dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl) argument
[all...] |
| H A D | aco_opt_value_numbering.cpp | 179 aDPP.bank_mask == bDPP.bank_mask && aDPP.row_mask == bDPP.row_mask &&
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| H A D | aco_print_ir.cpp | 599 if (dpp.row_mask != 0xf)
600 fprintf(output, " row_mask:0x%.1x", dpp.row_mask);
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| H A D | aco_optimizer_postRA.cpp | 416 assert(mov->dpp().row_mask == 0xf && mov->dpp().bank_mask == 0xf);
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| H A D | aco_ir.cpp | 350 dpp->row_mask = 0xf;
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| H A D | aco_assembler.cpp | 678 uint32_t encoding = (0xF & dpp.row_mask) << 28;
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| H A D | aco_optimizer.cpp | 1430 assert(instr->dpp().row_mask == 0xf && instr->dpp().bank_mask == 0xf);
2106 new_dpp->row_mask = cmp_dpp.row_mask;
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| H A D | aco_ir.h | 1412 uint8_t row_mask : 4; member in struct:aco::DPP_instruction
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| H A D | ac_llvm_build.c | 3514 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask,
3522 LLVMConstInt(ctx->i32, row_mask, 0),
3530 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask,
3539 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask,
3558 row_mask,
3513 _ac_build_dpp(struct ac_llvm_context * ctx,LLVMValueRef old,LLVMValueRef src,enum dpp_ctrl dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl) argument
3529 ac_build_dpp(struct ac_llvm_context * ctx,LLVMValueRef old,LLVMValueRef src,enum dpp_ctrl dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl) argument
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| /xsrc/external/mit/MesaLib/dist/src/amd/llvm/ |
| H A D | ac_llvm_build.c | 3519 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask,
3531 LLVMConstInt(ctx->i32, row_mask, 0), LLVMConstInt(ctx->i32, bank_mask, 0),
3539 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask,
3557 _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl);
3562 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl);
3518 _ac_build_dpp(struct ac_llvm_context * ctx,LLVMValueRef old,LLVMValueRef src,enum dpp_ctrl dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl) argument
3538 ac_build_dpp(struct ac_llvm_context * ctx,LLVMValueRef old,LLVMValueRef src,enum dpp_ctrl dpp_ctrl,unsigned row_mask,unsigned bank_mask,bool bound_ctrl) argument
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