Searched refs:rsrc1 (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_binary.h48 unsigned rsrc1; member in struct:ac_shader_config
H A Dac_binary.c62 conf->rsrc1 = value;
H A Dac_rtld.c556 assert(config->rsrc1 == 0 && config->rsrc2 == 0);
557 config->rsrc1 = c.rsrc1;
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_statistics.cpp103 BlockCycleEstimator::resource rsrc1; member in struct:aco::perf_info
192 if (perf.rsrc1 != resource_count) {
193 res_available[(int)perf.rsrc1] = cur_cycle + perf.cost1;
194 res_usage[(int)perf.rsrc1] += perf.cost1;
206 if (perf.rsrc1 != resource_count)
207 cost = MAX2(cost, res_available[(int)perf.rsrc1] - cur_cycle);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_pipeline_cache.c37 uint32_t rsrc1, rsrc2; member in struct:cache_entry_variant_info
327 variant->rsrc1 = info.rsrc1;
416 info.rsrc1 = variants[i]->rsrc1;
H A Dradv_shader.c469 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
533 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
538 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
540 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
H A Dradv_shader.h316 unsigned rsrc1; member in struct:radv_shader_variant
H A Dradv_pipeline.c2968 radeon_emit(cs, shader->rsrc1);
3027 radeon_emit(cs, shader->rsrc1);
3050 radeon_emit(cs, shader->rsrc1);
3068 radeon_emit(cs, shader->rsrc1);
3075 radeon_emit(cs, shader->rsrc1);
3194 radeon_emit(cs, gs->rsrc1);
3203 radeon_emit(cs, gs->rsrc1);
3360 radeon_emit(cs, ps->rsrc1);
3879 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
H A Dradv_device.c2600 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | local in function:radv_get_preamble_cs
2603 map[1] = rsrc1;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute.c71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; local in function:code_object_to_config
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
168 shader->config.rsrc1 =
497 radeon_emit(cs, config->rsrc1);
501 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
H A Dsi_shader.h574 unsigned rsrc1; member in struct:si_shader_config
H A Dsi_state_draw.c278 radeon_emit(cs, ls_current->config.rsrc1);
H A Dsi_state_shaders.c494 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
H A Dsi_shader.c5104 conf->rsrc1 = value;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute.c97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; local in function:code_object_to_config
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
195 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
204 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
544 radeon_emit(config->rsrc1);
550 config->rsrc1, config->rsrc2);
H A Dsi_state_shaders.c542 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
923 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | local in function:si_shader_gs
937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
1513 uint32_t rsrc1 = local in function:si_shader_vs
1527 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1537 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1733 uint32_t rsrc1 = local in function:si_shader_ps
1739 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1742 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
[all...]
H A Dsi_state_draw.cpp740 radeon_emit(ls_current->config.rsrc1);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_shader.c1367 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) |
1373 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
1382 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1393 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1416 config_out->rsrc1 |=
1422 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1449 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1455 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1460 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
1465 config_out->rsrc1 |
[all...]
H A Dradv_shader.h480 uint32_t rsrc1; member in struct:radv_shader_prolog
H A Dradv_pipeline.c4407 radeon_emit(cs, shader->config.rsrc1);
4480 radeon_emit(cs, shader->config.rsrc1);
4500 radeon_emit(cs, shader->config.rsrc1);
4520 radeon_emit(cs, shader->config.rsrc1);
4659 radeon_emit(cs, shader->config.rsrc1);
4665 radeon_emit(cs, shader->config.rsrc1);
4856 radeon_emit(cs, gs->config.rsrc1);
4866 radeon_emit(cs, gs->config.rsrc1);
5072 radeon_emit(cs, ps->config.rsrc1);
5663 radeon_emit(cs, shader->config.rsrc1);
[all...]
H A Dradv_cmd_buffer.c2883 uint32_t rsrc1 = vs_shader->config.rsrc1; local in function:emit_prolog_regs
2884 if (chip < GFX10 && G_00B228_SGPRS(prolog->rsrc1) > G_00B228_SGPRS(vs_shader->config.rsrc1))
2885 rsrc1 = (rsrc1 & C_00B228_SGPRS) | (prolog->rsrc1 & ~C_00B228_SGPRS);
2890 assert(G_00B848_VGPRS(vs_shader->config.rsrc1) >= G_00B848_VGPRS(prolog->rsrc1));
2913 radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);
[all...]
H A Dradv_device.c3930 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); local in function:radv_get_preamble_cs
3932 map[1] = rsrc1;

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