Searched refs:sampler_reg (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h234 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
236 FS_OUT(_i915_fs_texld(T0_TEXLD, dest_reg, sampler_reg, address_reg)); \
239 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
241 FS_OUT(_i915_fs_texld(T0_TEXLDP, dest_reg, sampler_reg, address_reg)); \
245 _i915_fs_texld(int load_op, int dest_reg, int sampler_reg, int address_reg) argument
253 if (REG_TYPE(sampler_reg) != REG_TYPE_S)
259 op.ui[0] |= REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h367 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
372 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
378 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
383 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h367 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
372 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
378 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
383 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1214 #define gen3_fs_texld(dest_reg, sampler_reg, address_reg) \
1219 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
1225 #define gen3_fs_texldp(dest_reg, sampler_reg, address_reg) \
1230 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1214 #define gen3_fs_texld(dest_reg, sampler_reg, address_reg) \
1219 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
1225 #define gen3_fs_texldp(dest_reg, sampler_reg, address_reg) \
1230 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_generator.cpp299 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD)); local in function:generate_tex
305 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
306 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
308 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
309 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
311 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
H A Dbrw_vec4.h275 src_reg sampler_reg);
H A Dbrw_vec4_visitor.cpp925 src_reg sampler_reg)
971 is_high_sampler(sampler_reg)) ? 1 : 0;
978 inst->src[2] = sampler_reg;
912 emit_texture(ir_texture_opcode op,dst_reg dest,const glsl_type * dest_type,src_reg coordinate,int coord_components,src_reg shadow_comparator,src_reg lod,src_reg lod2,src_reg sample_index,uint32_t constant_offset,src_reg offset_value,src_reg mcs,uint32_t surface,src_reg surface_reg,src_reg sampler_reg) argument
H A Dbrw_vec4_nir.cpp1988 src_reg sampler_reg = brw_imm_ud(sampler); local in function:brw::vec4_visitor::nir_emit_texture
2085 sampler_reg = emit_uniformize(temp);
2130 texture, texture_reg, sampler_reg);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_generator.cpp301 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD)); local in function:generate_tex
307 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
308 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
310 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
311 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
313 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
H A Dbrw_vec4.h272 src_reg sampler_reg);
H A Dbrw_vec4_visitor.cpp841 src_reg sampler_reg)
885 is_high_sampler(sampler_reg)) ? 1 : 0;
892 inst->src[2] = sampler_reg;
828 emit_texture(ir_texture_opcode op,dst_reg dest,int dest_components,src_reg coordinate,int coord_components,src_reg shadow_comparator,src_reg lod,src_reg lod2,src_reg sample_index,uint32_t constant_offset,src_reg offset_value,src_reg mcs,uint32_t surface,src_reg surface_reg,src_reg sampler_reg) argument
H A Dbrw_vec4_nir.cpp1990 src_reg sampler_reg = brw_imm_ud(sampler); local in function:brw::vec4_visitor::nir_emit_texture
2084 sampler_reg = emit_uniformize(temp);
2130 texture, texture_reg, sampler_reg);
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_structs.h579 unsigned sampler_reg:4; member in struct:texture_inst::__anonea2082432408
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_structs.h579 unsigned sampler_reg:4; member in struct:texture_inst::__anona54546772408
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_structs.h616 unsigned sampler_reg : 4; member in struct:texture_inst::__anon8e8c39662508
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c2065 unsigned sampler_reg,
2068 unsigned unit = inst->Src[sampler_reg].Register.Index;
2181 uint32_t comp_val = inst->Src[sampler_reg].Register.SwizzleX;
2061 emit_tex(struct lp_build_tgsi_soa_context * bld,const struct tgsi_full_instruction * inst,enum lp_build_tex_modifier modifier,LLVMValueRef * texel,unsigned sampler_reg,enum lp_sampler_op_type sampler_op) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c2085 unsigned sampler_reg,
2088 unsigned unit = inst->Src[sampler_reg].Register.Index;
2081 emit_tex(struct lp_build_tgsi_soa_context * bld,const struct tgsi_full_instruction * inst,enum lp_build_tex_modifier modifier,LLVMValueRef * texel,unsigned sampler_reg,enum lp_sampler_op_type sampler_op) argument

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