Searched refs:scalar (Results 1 - 25 of 97) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_opt_uniform_atomics.c84 get_dim(nir_ssa_scalar scalar) argument
86 if (!scalar.def->divergent)
89 if (scalar.def->parent_instr->type == nir_instr_type_intrinsic) {
90 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(scalar.def->parent_instr);
96 return 1 << scalar.comp;
100 return 1 << scalar.comp;
101 } else if (nir_ssa_scalar_is_alu(scalar)) {
102 if (nir_ssa_scalar_alu_op(scalar) == nir_op_iadd ||
103 nir_ssa_scalar_alu_op(scalar) == nir_op_imul) {
104 nir_ssa_scalar src0 = nir_ssa_scalar_chase_alu_src(scalar,
129 match_invocation_comparison(nir_ssa_scalar scalar) argument
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H A Dnir_opt_fragdepth.c37 nir_ssa_scalar scalar = nir_ssa_scalar_resolved(def, 0); local in function:ssa_def_is_source_depth
38 nir_instr *instr = scalar.def->parent_instr;
47 return scalar.comp == 2;
H A Dnir_lower_array_deref_of_vec.c150 nir_ssa_def *scalar = local in function:nir_lower_array_deref_of_vec_impl
152 if (scalar->parent_instr->type == nir_instr_type_ssa_undef) {
154 scalar);
158 scalar,
159 scalar->parent_instr);
H A Dnir_range_analysis.c1207 search_phi_bcsel(nir_ssa_scalar scalar, nir_ssa_scalar *buf, unsigned buf_size, struct set *visited) argument
1209 if (_mesa_set_search(visited, scalar.def))
1211 _mesa_set_add(visited, scalar.def);
1213 if (scalar.def->parent_instr->type == nir_instr_type_phi) {
1214 nir_phi_instr *phi = nir_instr_as_phi(scalar.def->parent_instr);
1230 if (nir_ssa_scalar_is_alu(scalar)) {
1231 nir_op op = nir_ssa_scalar_alu_op(scalar);
1234 nir_ssa_scalar src0 = nir_ssa_scalar_chase_alu_src(scalar, 0);
1235 nir_ssa_scalar src1 = nir_ssa_scalar_chase_alu_src(scalar, 1);
1244 buf[0] = scalar;
1271 nir_unsigned_upper_bound(nir_shader * shader,struct hash_table * range_ht,nir_ssa_scalar scalar,const nir_unsigned_upper_bound_config * config) argument
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/xsrc/external/mit/brotli/dist/c/common/
H A Dtransform.c195 /* Limited sign extension: scalar < (1 << 24). */
196 uint32_t scalar = local in function:Shift
199 /* 1-byte rune / 0sssssss / 7 bit scalar (ASCII). */
200 scalar += (uint32_t)word[0];
201 word[0] = (uint8_t)(scalar & 0x7Fu);
207 /* 2-byte rune / 110sssss AAssssss / 11 bit scalar. */
209 scalar += (uint32_t)((word[1] & 0x3Fu) | ((word[0] & 0x1Fu) << 6u));
210 word[0] = (uint8_t)(0xC0 | ((scalar >> 6u) & 0x1F));
211 word[1] = (uint8_t)((word[1] & 0xC0) | (scalar & 0x3F));
214 /* 3-byte rune / 1110ssss AAssssss BBssssss / 16 bit scalar
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_swizzle.h53 LLVMValueRef scalar);
58 LLVMValueRef scalar);
H A Dlp_bld_swizzle.c49 LLVMValueRef scalar)
54 /* scalar */
55 assert(vec_type == LLVMTypeOf(scalar));
56 res = scalar;
65 assert(LLVMGetElementType(vec_type) == LLVMTypeOf(scalar));
67 res = LLVMBuildInsertElement(builder, undef, scalar, LLVMConstNull(i32_type), "");
80 LLVMValueRef scalar)
82 assert(lp_check_elem_type(bld->type, LLVMTypeOf(scalar)));
84 return lp_build_broadcast(bld->gallivm, bld->vec_type, scalar);
110 * Trivial scalar
47 lp_build_broadcast(struct gallivm_state * gallivm,LLVMTypeRef vec_type,LLVMValueRef scalar) argument
79 lp_build_broadcast_scalar(struct lp_build_context * bld,LLVMValueRef scalar) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_swizzle.h53 LLVMValueRef scalar);
58 LLVMValueRef scalar);
H A Dlp_bld_swizzle.c50 LLVMValueRef scalar)
55 /* scalar */
56 assert(vec_type == LLVMTypeOf(scalar));
57 res = scalar;
66 assert(LLVMGetElementType(vec_type) == LLVMTypeOf(scalar));
68 res = LLVMBuildInsertElement(builder, undef, scalar, LLVMConstNull(i32_type), "");
81 LLVMValueRef scalar)
83 assert(lp_check_elem_type(bld->type, LLVMTypeOf(scalar)));
85 return lp_build_broadcast(bld->gallivm, bld->vec_type, scalar);
111 * Trivial scalar
48 lp_build_broadcast(struct gallivm_state * gallivm,LLVMTypeRef vec_type,LLVMValueRef scalar) argument
80 lp_build_broadcast_scalar(struct lp_build_context * bld,LLVMValueRef scalar) argument
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/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir_lower_array_deref_of_vec.c145 nir_ssa_def *scalar = local in function:nir_lower_array_deref_of_vec_impl
147 if (scalar->parent_instr->type == nir_instr_type_ssa_undef) {
149 nir_src_for_ssa(scalar));
153 nir_src_for_ssa(scalar),
154 scalar->parent_instr);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/
H A Ddisasm.c589 if (combine->scalar.dest_vec &&
590 combine->scalar.arg1_en) {
591 /* This particular combination can only be valid for scalar * vector
596 asm_op op = combine_ops[combine->scalar.op];
601 printf("op%u", combine->scalar.op);
604 if (!combine->scalar.dest_vec)
605 print_outmod(combine->scalar.dest_modifier);
608 if (combine->scalar.dest_vec) {
612 print_dest_scalar(combine->scalar.dest);
616 print_source_scalar(combine->scalar
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H A Dcodegen.c441 f->scalar.dest_vec = false;
442 f->scalar.arg1_en = false;
447 f->scalar.dest = ppir_target_get_dest_reg_index(dest) + dest_component;
448 f->scalar.dest_modifier = dest->modifier;
451 f->scalar.arg0_src = get_scl_reg_index(src, dest_component);
452 f->scalar.arg0_absolute = src->absolute;
453 f->scalar.arg0_negate = src->negate;
457 f->scalar.op = ppir_codegen_combine_scalar_op_rsqrt;
460 f->scalar.op = ppir_codegen_combine_scalar_op_log2;
463 f->scalar
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/pp/
H A Ddisasm.c624 if (combine->scalar.dest_vec &&
625 combine->scalar.arg1_en) {
626 /* This particular combination can only be valid for scalar * vector
631 asm_op op = combine_ops[combine->scalar.op];
636 fprintf(fp, "op%u", combine->scalar.op);
639 if (!combine->scalar.dest_vec)
640 print_outmod(combine->scalar.dest_modifier, fp);
643 if (combine->scalar.dest_vec) {
647 print_dest_scalar(combine->scalar.dest, fp);
651 print_source_scalar(combine->scalar
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H A Dcodegen.c505 f->scalar.dest_vec = false;
506 f->scalar.arg1_en = false;
511 f->scalar.dest = ppir_target_get_dest_reg_index(dest) + dest_component;
512 f->scalar.dest_modifier = dest->modifier;
515 f->scalar.arg0_src = get_scl_reg_index(src, dest_component);
516 f->scalar.arg0_absolute = src->absolute;
517 f->scalar.arg0_negate = src->negate;
521 f->scalar.op = ppir_codegen_combine_scalar_op_rsqrt;
524 f->scalar.op = ppir_codegen_combine_scalar_op_log2;
527 f->scalar
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/clover/llvm/codegen/
H A Dcommon.cpp106 args.emplace_back(module::argument::scalar, sizeof(cl_uint),
114 args.emplace_back(module::argument::scalar, sizeof(cl_uint),
152 args.emplace_back(module::argument::scalar, arg_api_size,
163 args.emplace_back(module::argument::scalar, sizeof(cl_uint),
169 args.emplace_back(module::argument::scalar, sizeof(cl_uint),
/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/clover/core/core/
H A Dmodule.hpp58 scalar, enumerator in enum:clover::module::argument::type
95 argument() : type(scalar), size(0),
/xsrc/external/mit/MesaLib/dist/src/asahi/lib/
H A Dagx_device.h99 agx_submit_cmdbuf(struct agx_device *dev, unsigned cmdbuf, unsigned mappings, uint64_t scalar);
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/clover/llvm/codegen/
H A Dcommon.cpp188 args.emplace_back(binary::argument::scalar, sizeof(cl_uint),
196 args.emplace_back(binary::argument::scalar, sizeof(cl_uint),
239 args.emplace_back(binary::argument::scalar, arg_api_size,
260 args.emplace_back(binary::argument::scalar, sizeof(cl_uint),
266 args.emplace_back(binary::argument::scalar, sizeof(cl_uint),
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/clover/core/
H A Dbinary.hpp84 scalar, enumerator in enum:clover::binary::argument::type
121 argument() : type(scalar), size(0),
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/
H A Dir3-notes.rst6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or nops). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
13 Here, the second instruction needs the output of the first group of scalar instructions in the wrong order, resulting in not enough instruction spots between the ``add r0.w, r1.w, r2.w`` and ``mul r0.x, r1.x, r0.w``. Which is why the original (old) compiler which merely translated nearly literally from TGSI to ir3, had a strong tendency to fall over.
167 Groups registers which need to be assigned to consecutive scalar
175 scalar components to be consumed by other instructions.
191 Certain instructions, such as texture sample instructions, consume multiple consecutive scalar registers via a single src register encoded in the instruction, and/or write multiple consecutive scalar registers. In the simplest example:
220 The frontend sets up the SSA ptrs from ``sam`` source register to the ``fanin`` meta instruction, which in turn points to the instructions producing the ``coord.x`` and ``coord.y`` values. And the grouping_ pass sets up the ``left`` and ``right`` neighbor pointers to the ``fanin``\'s sources, used later by the `register assignment`_ pass to assign blocks of scalar registers.
222 And likewise, for the consecutive scalar registers for the destination:
265 But relative addressing of gpr file (which can be as src or dst) has additional restrictions on register assignment (ie. the array elements must be assigned to consecutive scalar register
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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_statistics.cpp51 scalar, enumerator in enum:aco::BlockCycleEstimator::resource
133 case instr_class::salu: return {2, WAIT_USE(scalar, 1)};
134 case instr_class::smem: return {0, WAIT_USE(scalar, 1)};
161 case instr_class::salu: return {4, WAIT_USE(scalar, 4)};
162 case instr_class::smem: return {4, WAIT_USE(scalar, 4)};
554 fprintf(stderr, "salu_smem_usage: %f\n", usage[(int)BlockCycleEstimator::scalar]);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_insn.c152 * Apply a "scalar" swizzle to a src_register returning a new
154 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
157 scalar(struct src_register src, unsigned comp) function in typeref:struct:src_register
1004 return scalar(reg, swizzle);
1073 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
1180 * RCP is scalar in SVGA3D:
1188 scalar(src1, i) ))
1227 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1228 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1247 src0 = scalar(src
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/
H A Dst_glsl_to_nir.cpp304 st_nir_opts(nir_shader *nir, bool scalar) argument
312 if (scalar) {
634 st_nir_link_shaders(nir_shader **producer, nir_shader **consumer, bool scalar) argument
636 if (scalar) {
643 st_nir_opts(*producer, scalar);
644 st_nir_opts(*consumer, scalar);
647 st_nir_opts(*consumer, scalar);
672 st_nir_opts(*producer, scalar);
673 st_nir_opts(*consumer, scalar);
755 /* Determine scalar propert
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_tgsi_insn.c152 * Apply a "scalar" swizzle to a src_register returning a new
154 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
157 scalar(struct src_register src, unsigned comp) function in typeref:struct:src_register
1002 return scalar(reg, swizzle);
1071 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
1178 * RCP is scalar in SVGA3D:
1186 scalar(src1, i) ))
1225 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1226 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1245 src0 = scalar(src
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/xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/
H A Dir3-notes.rst6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
13 Here, the second instruction needs the output of the first group of scalar instructions in the wrong order, resulting in not enough instruction spots between the ``add r0.w, r1.w, r2.w`` and ``mul r0.x, r1.x, r0.w``. Which is why the original (old) compiler which merely translated nearly literally from TGSI to ir3, had a strong tendency to fall over.
167 Groups registers which need to be assigned to consecutive scalar
175 scalar components to be consumed by other instructions.
191 Certain instructions, such as texture sample instructions, consume multiple consecutive scalar registers via a single src register encoded in the instruction, and/or write multiple consecutive scalar registers. In the simplest example:
220 The frontend sets up the SSA ptrs from ``sam`` source register to the ``collect`` meta instruction, which in turn points to the instructions producing the ``coord.x`` and ``coord.y`` values. And the grouping_ pass sets up the ``left`` and ``right`` neighbor pointers to the ``collect``\'s sources, used later by the `register assignment`_ pass to assign blocks of scalar registers.
222 And likewise, for the consecutive scalar registers for the destination:
265 But relative addressing of gpr file (which can be as src or dst) has additional restrictions on register assignment (i.e. the array elements must be assigned to consecutive scalar register
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