| /xsrc/external/mit/libXdmcp/dist/ |
| H A D | Wrap.h | 12 extern void _XdmcpAuthSetup (auth_cblock key, auth_wrapper_schedule schedule);
14 auth_wrapper_schedule schedule, int edflag);
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| H A D | Unwrap.c | 65 auth_wrapper_schedule schedule; local in function:XdmcpUnwrap
68 _XdmcpAuthSetup (expand_wrapper, schedule);
77 _XdmcpAuthDoIt ((unsigned char *) (input + j), (unsigned char *) tmp, schedule, 0);
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| H A D | Wrap.c | 59 auth_wrapper_schedule schedule; local in function:XdmcpWrap
62 _XdmcpAuthSetup (expand_wrapper, schedule);
83 _XdmcpAuthDoIt (tmp, (output + j), schedule, 1);
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| H A D | Wraphelp.c | 372 void _XdmcpAuthSetup(auth_cblock key, auth_wrapper_schedule schedule) argument
379 k=(CARD32 *)schedule;
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| /xsrc/external/mit/MesaLib/dist/docs/ |
| H A D | release-calendar.rst | 12 Regular updates will ensure that the schedule for the current and the
19 The way the release schedule works is explained
20 :ref:`here <schedule>`.
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| H A D | releasing.rst | 24 Release schedule
31 the release schedule is planned, and the date and other details for
22 .. _schedule: target in section:Overview
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/ |
| H A D | ir3_postsched.c | 104 schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) function in typeref:typename:void
112 di(instr, "schedule");
157 /* Determine if this is an instruction that we'd prefer not to schedule
178 /* find instruction to schedule: */
199 /* Try to schedule inputs with a higher priority, if possible, as
287 * bit (but we probably do want to schedule some other instructions
660 /* First schedule all meta:input instructions, followed by
671 schedule(ctx, instr);
675 schedule(ctx, instr);
693 schedule(ct
[all...] |
| H A D | ir3_sched.c | 77 * to schedule any remaining instructions that use that value first.
131 /* For instructions that are a meta:collect src, once we schedule
135 * RA, and realize that as soon as we schedule the first collect
136 * src, there is no penalty to schedule the remainder (ie. they
138 * schedule the rest ASAP to minimize the live range of the vecN.
157 * Which we'd prefer to schedule as late as possible, since it
256 schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr) function in typeref:typename:void
281 di(instr, "schedule");
323 * If we can, we'd like to try to schedule another texture fetch
364 /* Check if instruction is ok to schedule
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| /xsrc/external/mit/xdm/dist/xdm/ |
| H A D | genauth.c | 402 auth_wrapper_schedule schedule; local in function:GenerateAuthData
430 _XdmcpAuthSetup (key, schedule);
434 _XdmcpAuthDoIt (data, data, schedule, 1);
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| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/ |
| H A D | ir3_sched.c | 36 * instruction to schedule from the deepest instruction (recursing through
49 * to schedule any remaining instructions that use that value first.
119 * we just track it per block (because we schedule a block at a time) and
150 schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr) function in typeref:typename:void
351 /* Check if instruction is ok to schedule. Make sure it is not blocked
408 * to schedule the bary.f's outside of any block which
428 /* Find the best instruction to schedule from specified instruction or
487 /* find instruction to schedule: */
633 /* first a pre-pass to schedule all meta:input instructions
639 schedule(ct
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/ |
| H A D | ir3-notes.rst | 6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or nops). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
15 So the current compiler instead, in the frontend, generates a directed-acyclic-graph of instructions and basic blocks, which go through various additional passes to eventually schedule and do register assignment.
39 stages to schedule and do register assignment.
263 Relative addressing of the const file (for example, a uniform array) is relatively simple. We don't do register assignment of the const file, so all that is required is to schedule things properly. Ie. the instruction that writes the address register must be scheduled first, and we cannot have two different address register values live at one time.
293 The scheduling pass has some smarts to schedule things such that only a single ``a0.x`` value is used at any one time.
423 After the grouping_ pass, there are no more instructions to insert or remove. Start scheduling each basic block from the deepest node in the depth sorted list created by the depth_ pass, recursively trying to schedule each instruction after it's source instructions plus delay slots. Insert ``nop``\s as required.
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| /xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/ |
| H A D | ir3-notes.rst | 6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
15 So the current compiler instead, in the frontend, generates a directed-acyclic-graph of instructions and basic blocks, which go through various additional passes to eventually schedule and do register assignment.
39 stages to schedule and do register assignment.
263 Relative addressing of the const file (for example, a uniform array) is relatively simple. We don't do register assignment of the const file, so all that is required is to schedule things properly. I.e. the instruction that writes the address register must be scheduled first, and we cannot have two different address register values live at one time.
293 The scheduling pass has some smarts to schedule things such that only a single ``a0.x`` value is used at any one time.
394 After the grouping_ pass, there are no more instructions to insert or remove. Start scheduling each basic block from the deepest node in the depth sorted list created by the depth_ pass, recursively trying to schedule each instruction after its source instructions plus delay slots. Insert ``nop``\s as required.
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/swrast/ |
| H A D | s_aatritemp.h | 186 #pragma omp parallel for schedule(dynamic) private(iy) firstprivate(span)
255 #pragma omp parallel for schedule(dynamic) private(iy) firstprivate(span)
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| /xsrc/external/mit/MesaLib/dist/src/mesa/swrast/ |
| H A D | s_aatritemp.h | 186 #pragma omp parallel for schedule(dynamic) private(iy) firstprivate(span)
255 #pragma omp parallel for schedule(dynamic) private(iy) firstprivate(span)
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README.md | 12 3. Issues can be fixed within mesa releases, independently of the schedule of other projects.
85 Scheduling is another NP-complete problem where basically all known heuristics suffer from unpredictable change in register pressure. For that reason, the implemented scheduler does not completely re-schedule all instructions, but only aims to move up memory loads as far as possible without exceeding the maximum register limit for the pre-calculated wave count. The reason this works is that ILP is very limited on GCN. This approach looks promising so far.
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 11.2.0.rst | 141 Tonga VM Faults since llvm ScheduleDAGInstrs: Rework schedule graph
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| H A D | 18.2.0.rst | 127 - r600/sb: optimizer tries to schedule access to different array
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| H A D | 20.2.0.rst | 361 - pan/bi: Don't schedule <32-bit IMATH to FMA
640 - pan/mdg: Prefer type over regmode for schedule constraints
3633 - nir/schedule: Store a pointer to the scoreboard in nir_deps_state
3651 - nir/schedule: Store a pointer to the options struct in scoreboard
3652 - nir/schedule: Add a callback for backend-specific dependencies
3654 - nir/schedule: Add an option for a fallback scheduling algorithm
|
| H A D | 21.0.0.rst | 816 - aco: allow to schedule SALU/SMEM through exec changes
818 - aco: schedule position exports in the same pass as memory operations
1005 - docs: add release schedule for 20.3
|
| H A D | 21.1.0.rst | 494 - pan/bi: Choose instructions to schedule
495 - pan/bi: Destructively schedule a single instruction
1324 - ir3/postsched: Make sure to schedule inputs before kill
1329 - ir3/sched: Don't schedule too many tex/SFU instructions
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| H A D | 19.3.0.rst | 312 - pan/midgard: Add post-schedule iteration helpers
806 - aco: don't schedule instructions through depending VMEM instructions
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| H A D | 21.2.0.rst | 449 - pan/bi: Don't schedule clamps to +FADD.v2f16
1460 - ir3/sched: Don't schedule collect early
2182 - docs/release-calendar: add the schedule for the 21.1 branch
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| H A D | 19.0.0.rst | 306 - docs: complete the calendar and release schedule documentation
|
| H A D | 20.0.0.rst | 347 - pan/midgard: Add schedule barrier after fragment writeout
|
| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | 28444 "description": "docs: add 21.3.x release schedule",
[all...] |