Searched refs:sctx (Results 1 - 25 of 98) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_streamout.c29 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
68 void si_streamout_buffers_dirty(struct si_context *sctx) argument
70 if (!sctx->streamout.enabled_mask)
73 si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_begin);
74 si_set_streamout_enable(sctx, true);
81 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_streamout_targets
82 unsigned old_num_targets = sctx->streamout.num_targets;
87 if (sctx->streamout.num_targets && sctx
214 gfx10_emit_streamout_begin(struct si_context * sctx) argument
257 gfx10_emit_streamout_end(struct si_context * sctx) argument
277 si_flush_vgt_streamout(struct si_context * sctx) argument
306 si_emit_streamout_begin(struct si_context * sctx) argument
360 si_emit_streamout_end(struct si_context * sctx) argument
412 si_emit_streamout_enable(struct si_context * sctx) argument
427 si_set_streamout_enable(struct si_context * sctx,bool enable) argument
444 si_update_prims_generated_query_state(struct si_context * sctx,unsigned type,int diff) argument
464 si_init_streamout_functions(struct si_context * sctx) argument
[all...]
H A Dsi_state_draw.cpp53 static void si_emit_spi_map(struct si_context *sctx) argument
55 struct si_shader *ps = sctx->shader.ps.current;
64 struct si_shader *vs = si_get_vs(sctx)->current;
65 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
102 radeon_begin(&sctx->gfx_cs);
103 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
104 sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
105 radeon_end_update_context_roll(sctx);
109 static bool si_update_shaders(struct si_context *sctx) argument
111 struct pipe_context *ctx = (struct pipe_context *)sctx;
390 si_prefetch_shader_async(struct si_context * sctx,struct si_shader * shader) argument
408 si_prefetch_shaders(struct si_context * sctx) argument
510 si_emit_derived_tess_state(struct si_context * sctx,unsigned * num_patches) argument
912 si_init_ia_multi_vgt_param_table(struct si_context * sctx) argument
941 si_is_line_stipple_enabled(struct si_context * sctx) argument
976 si_get_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count) argument
1057 si_emit_rasterizer_prim_state(struct si_context * sctx) argument
1109 si_emit_vs_state(struct si_context * sctx,unsigned index_size) argument
1154 si_prim_restart_index_changed(struct si_context * sctx,bool primitive_restart,unsigned restart_index) argument
1163 si_emit_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count) argument
1201 gfx10_emit_ge_cntl(struct si_context * sctx,unsigned num_patches) argument
1248 si_emit_draw_registers(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum pipe_prim_type prim,unsigned num_patches,unsigned instance_count,bool primitive_restart,unsigned restart_index,unsigned min_vertex_count) argument
1311 si_emit_draw_packets(struct si_context * sctx,const struct pipe_draw_info * info,unsigned drawid_base,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned total_count,struct pipe_resource * indexbuf,unsigned index_size,unsigned index_offset,unsigned instance_count,unsigned original_index_size) argument
1763 si_upload_and_prefetch_VB_descriptors(struct si_context * sctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask) argument
1911 si_get_draw_start_count(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned * start,unsigned * count) argument
1985 si_emit_all_states(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect,enum pipe_prim_type prim,unsigned instance_count,unsigned min_vertex_count,bool primitive_restart,unsigned skip_atom_mask) argument
2053 struct si_context *sctx = (struct si_context *)ctx; local in function:si_draw
2537 struct si_context *sctx = (struct si_context *)pipe; local in function:si_draw_rectangle
2575 si_init_draw_vbo(struct si_context * sctx) argument
2593 si_init_draw_vbo_all_pipeline_options(struct si_context * sctx) argument
2645 si_init_spi_map_functions(struct si_context * sctx) argument
[all...]
H A Dsi_pipe.c185 struct si_context *sctx = (struct si_context *)context; local in function:si_destroy_context
195 si_release_all_descriptors(sctx);
197 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
198 gfx10_destroy_query(sctx);
200 if (sctx->thread_trace)
201 si_destroy_thread_trace(sctx);
203 pipe_resource_reference(&sctx->esgs_ring, NULL);
204 pipe_resource_reference(&sctx->gsvs_ring, NULL);
205 pipe_resource_reference(&sctx
356 struct si_context *sctx = (struct si_context *)ctx; local in function:si_get_reset_status
375 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_device_reset_callback
393 struct si_context *sctx = (struct si_context *)ctx; local in function:si_emit_string_marker
406 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_debug_callback
420 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_log_context
442 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_frontend_noop
457 struct si_context *sctx = CALLOC_STRUCT(si_context); local in function:si_create_context
967 struct si_context *sctx = (struct si_context *)ctx; local in function:si_test_vmfault
990 si_test_gds_memory_management(struct si_context * sctx,unsigned alloc_size,unsigned alignment,enum radeon_bo_domain domain) argument
[all...]
H A Dsi_cp_reg_shadowing.c69 si_create_shadowing_ib_preamble(struct si_context *sctx) argument
73 if (sctx->screen->dpbb_allowed) {
86 if (sctx->chip_class >= GFX10) {
100 } else if (sctx->chip_class == GFX9) {
136 si_build_load_reg(sctx->screen, pm4, i, sctx->shadowed_regs);
150 void si_init_cp_reg_shadowing(struct si_context *sctx) argument
152 if (sctx->screen->info.mid_command_buffer_preemption_enabled ||
153 sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
154 sctx
[all...]
H A Dsi_state_binning.c63 static struct uvec2 si_get_color_bin_size(struct si_context *sctx, unsigned cb_target_enabled_4bit) argument
65 unsigned num_fragments = sctx->framebuffer.nr_color_samples;
69 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
73 struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture;
79 if (si_get_ps_iter_samples(sctx) >= 2)
174 return si_find_bin_size(sctx->screen, table, sum);
177 static struct uvec2 si_get_depth_bin_size(struct si_context *sctx) argument
179 struct si_state_dsa *dsa = sctx->queued.named.dsa;
181 if (!sctx->framebuffer.state.zsbuf || (!dsa->depth_enabled && !dsa->stencil_enabled)) {
187 struct si_texture *tex = (struct si_texture *)sctx
302 gfx10_get_bin_sizes(struct si_context * sctx,unsigned cb_target_enabled_4bit,struct uvec2 * color_bin_size,struct uvec2 * depth_bin_size) argument
405 si_emit_dpbb_disable(struct si_context * sctx) argument
443 si_emit_dpbb_state(struct si_context * sctx) argument
[all...]
H A Dsi_sqtt.c37 si_emit_spi_config_cntl(struct si_context* sctx,
41 si_thread_trace_init_bo(struct si_context *sctx) argument
43 unsigned max_se = sctx->screen->info.max_se;
44 struct radeon_winsys *ws = sctx->ws;
50 sctx->thread_trace->buffer_size = align64(sctx->thread_trace->buffer_size,
56 size += sctx->thread_trace->buffer_size * (uint64_t)max_se;
58 sctx->thread_trace->bo =
64 if (!sctx->thread_trace->bo)
71 si_se_is_disabled(struct si_context* sctx, unsigne argument
79 si_emit_thread_trace_start(struct si_context * sctx,struct radeon_cmdbuf * cs,uint32_t queue_family_index) argument
243 si_copy_thread_trace_info_regs(struct si_context * sctx,struct radeon_cmdbuf * cs,unsigned se_index) argument
284 si_emit_thread_trace_stop(struct si_context * sctx,struct radeon_cmdbuf * cs,uint32_t queue_family_index) argument
368 si_thread_trace_start(struct si_context * sctx,int family,struct radeon_cmdbuf * cs) argument
411 si_thread_trace_stop(struct si_context * sctx,int family,struct radeon_cmdbuf * cs) argument
455 si_thread_trace_init_cs(struct si_context * sctx) argument
485 si_begin_thread_trace(struct si_context * sctx,struct radeon_cmdbuf * rcs) argument
492 si_end_thread_trace(struct si_context * sctx,struct radeon_cmdbuf * rcs) argument
499 si_get_thread_trace(struct si_context * sctx,struct ac_thread_trace * thread_trace) argument
560 si_init_thread_trace(struct si_context * sctx) argument
619 si_destroy_thread_trace(struct si_context * sctx) argument
670 si_handle_thread_trace(struct si_context * sctx,struct radeon_cmdbuf * rcs) argument
726 si_emit_thread_trace_userdata(struct si_context * sctx,struct radeon_cmdbuf * cs,const void * data,uint32_t num_dwords) argument
750 si_emit_spi_config_cntl(struct si_context * sctx,struct radeon_cmdbuf * cs,bool enable) argument
776 si_sqtt_write_event_marker(struct si_context * sctx,struct radeon_cmdbuf * rcs,enum rgp_sqtt_marker_event_type api_type,uint32_t vertex_offset_user_data,uint32_t instance_offset_user_data,uint32_t draw_index_user_data) argument
808 si_write_event_with_dims_marker(struct si_context * sctx,struct radeon_cmdbuf * rcs,enum rgp_sqtt_marker_event_type api_type,uint32_t x,uint32_t y,uint32_t z) argument
829 si_sqtt_describe_barrier_start(struct si_context * sctx,struct radeon_cmdbuf * rcs) argument
841 si_sqtt_describe_barrier_end(struct si_context * sctx,struct radeon_cmdbuf * rcs,unsigned flags) argument
881 si_write_user_event(struct si_context * sctx,struct radeon_cmdbuf * rcs,enum rgp_sqtt_marker_user_event_type type,const char * str,int len) argument
964 si_sqtt_add_code_object(struct si_context * sctx,uint64_t pipeline_hash,bool is_compute) argument
1034 si_sqtt_register_pipeline(struct si_context * sctx,uint64_t pipeline_hash,uint64_t base_address,bool is_compute) argument
1052 si_sqtt_describe_pipeline_bind(struct si_context * sctx,uint64_t pipeline_hash,int bind_point) argument
[all...]
H A Dsi_state.h382 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
465 #define si_pm4_state_changed(sctx, member) \
466 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
468 #define si_pm4_state_enabled_and_changed(sctx, member) \
469 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
471 #define si_pm4_bind_state(sctx, member, value) \
473 (sctx)->queued.named.member = (value); \
474 if (value && value != (sctx)
[all...]
H A Dsi_blit.c44 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op) argument
46 util_blitter_save_vertex_shader(sctx->blitter, sctx->shader.vs.cso);
47 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->shader.tcs.cso);
48 util_blitter_save_tesseval_shader(sctx->blitter, sctx->shader.tes.cso);
49 util_blitter_save_geometry_shader(sctx->blitter, sctx->shader.gs.cso);
50 util_blitter_save_so_targets(sctx
87 si_blitter_end(struct si_context * sctx) argument
116 si_blit_dbcb_copy(struct si_context * sctx,struct si_texture * src,struct si_texture * dst,unsigned planes,unsigned level_mask,unsigned first_layer,unsigned last_layer,unsigned first_sample,unsigned last_sample) argument
188 si_blit_decompress_zs_planes_in_place(struct si_context * sctx,struct si_texture * texture,unsigned planes,unsigned level_mask,unsigned first_layer,unsigned last_layer) argument
255 si_blit_decompress_zs_in_place(struct si_context * sctx,struct si_texture * texture,unsigned levels_z,unsigned levels_s,unsigned first_layer,unsigned last_layer) argument
281 si_decompress_depth(struct si_context * sctx,struct si_texture * tex,unsigned required_planes,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
398 si_decompress_sampler_depth_textures(struct si_context * sctx,struct si_samplers * textures) argument
432 si_blit_decompress_color(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,bool need_dcc_decompress,bool need_fmask_expand) argument
538 si_decompress_color_texture(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level,bool need_fmask_expand) argument
552 si_decompress_sampler_color_textures(struct si_context * sctx,struct si_samplers * textures) argument
574 si_decompress_image_color_textures(struct si_context * sctx,struct si_images * images) argument
595 si_check_render_feedback_texture(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
624 si_check_render_feedback_textures(struct si_context * sctx,struct si_samplers * textures,uint32_t in_use_mask) argument
646 si_check_render_feedback_images(struct si_context * sctx,struct si_images * images,uint32_t in_use_mask) argument
668 si_check_render_feedback_resident_textures(struct si_context * sctx) argument
685 si_check_render_feedback_resident_images(struct si_context * sctx) argument
702 si_check_render_feedback(struct si_context * sctx) argument
730 si_decompress_resident_textures(struct si_context * sctx) argument
753 si_decompress_resident_images(struct si_context * sctx) argument
765 si_decompress_textures(struct si_context * sctx,unsigned shader_mask) argument
834 struct si_context *sctx = (struct si_context *)ctx; local in function:si_decompress_subresource
881 si_use_compute_copy_for_float_formats(struct si_context * sctx,struct pipe_resource * texture,unsigned level) argument
907 struct si_context *sctx = (struct si_context *)ctx; local in function:si_resource_copy_region
1058 si_do_CB_resolve(struct si_context * sctx,const struct pipe_blit_info * info,struct pipe_resource * dst,unsigned dst_level,unsigned dst_z,enum pipe_format format) argument
1099 struct si_context *sctx = (struct si_context *)ctx; local in function:do_hardware_msaa_resolve
1226 struct si_context *sctx = (struct si_context *)ctx; local in function:si_blit
1305 struct si_context *sctx = (struct si_context *)ctx; local in function:si_generate_mipmap
1333 struct si_context *sctx = (struct si_context *)ctx; local in function:si_flush_resource
1349 si_flush_implicit_resources(struct si_context * sctx) argument
1358 si_decompress_dcc(struct si_context * sctx,struct si_texture * tex) argument
1411 si_init_blit_functions(struct si_context * sctx) argument
[all...]
H A Dsi_cp_dma.c43 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx) argument
46 sctx->chip_class >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u) : S_415_BYTE_COUNT_GFX6(~0u);
56 static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, uint64_t dst_va, argument
62 assert(size <= cp_dma_max_byte_count(sctx));
63 assert(sctx->chip_class != GFX6 || cache_policy == L2_BYPASS);
65 if (sctx->chip_class >= GFX9)
78 if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) && src_va == dst_va) {
84 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
95 } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
102 if (sctx
133 si_cp_dma_wait_for_idle(struct si_context * sctx,struct radeon_cmdbuf * cs) argument
144 si_cp_dma_prepare(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,unsigned byte_count,uint64_t remaining_size,unsigned user_flags,enum si_coherency coher,bool * is_first,unsigned * packet_flags) argument
188 si_cp_dma_clear_buffer(struct si_context * sctx,struct radeon_cmdbuf * cs,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy) argument
243 si_cp_dma_realign_engine(struct si_context * sctx,unsigned size,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy,bool * is_first) argument
280 si_cp_dma_copy_buffer(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,uint64_t dst_offset,uint64_t src_offset,unsigned size,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy) argument
392 si_cp_dma_prefetch(struct si_context * sctx,struct pipe_resource * buf,unsigned offset,unsigned size) argument
432 si_test_gds(struct si_context * sctx) argument
479 si_cp_write_data(struct si_context * sctx,struct si_resource * buf,unsigned offset,unsigned size,unsigned dst_sel,unsigned engine,const void * data) argument
502 si_cp_copy_data(struct si_context * sctx,struct radeon_cmdbuf * cs,unsigned dst_sel,struct si_resource * dst,unsigned dst_offset,unsigned src_sel,struct si_resource * src,unsigned src_offset) argument
[all...]
H A Dgfx10_query.c33 static void emit_shader_query(struct si_context *sctx) argument
35 assert(!list_is_empty(&sctx->shader_query_buffers));
38 list_last_entry(&sctx->shader_query_buffers, struct gfx10_sh_query_buffer, list);
42 static void gfx10_release_query_buffers(struct si_context *sctx, argument
57 if (qbuf->list.next == &sctx->shader_query_buffers)
59 if (qbuf->list.prev == &sctx->shader_query_buffers)
68 static bool gfx10_alloc_query_buffer(struct si_context *sctx) argument
70 if (si_is_atom_dirty(sctx, &sctx->atoms.s.shader_query))
75 if (!list_is_empty(&sctx
138 gfx10_sh_query_destroy(struct si_context * sctx,struct si_query * rquery) argument
145 gfx10_sh_query_begin(struct si_context * sctx,struct si_query * rquery) argument
164 gfx10_sh_query_end(struct si_context * sctx,struct si_query * rquery) argument
233 gfx10_sh_query_get_result(struct si_context * sctx,struct si_query * rquery,bool wait,union pipe_query_result * result) argument
278 gfx10_sh_query_get_result_resource(struct si_context * sctx,struct si_query * rquery,bool wait,enum pipe_query_value_type result_type,int index,struct pipe_resource * resource,unsigned offset) argument
440 gfx10_init_query(struct si_context * sctx) argument
446 gfx10_destroy_query(struct si_context * sctx) argument
[all...]
H A Dsi_compute.c228 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_compute_state
255 sel->compiler_ctx_state.debug = sctx->debug;
256 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
259 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
276 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
277 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
290 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_compute_state
294 sctx->cs_shader_state.program = program;
302 si_set_active_descriptors(sctx,
331 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_global_binding
367 si_emit_initial_compute_regs(struct si_context * sctx,struct radeon_cmdbuf * cs) argument
441 si_setup_compute_scratch_buffer(struct si_context * sctx,struct si_shader * shader,struct ac_shader_config * config) argument
475 si_switch_compute_shader(struct si_context * sctx,struct si_compute * program,struct si_shader * shader,const amd_kernel_code_t * code_object,unsigned offset,bool * prefetch) argument
568 setup_scratch_rsrc_user_sgprs(struct si_context * sctx,const amd_kernel_code_t * code_object,unsigned user_sgpr) argument
606 si_setup_user_sgprs_co_v2(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info,uint64_t kernel_args_va) argument
688 si_upload_compute_input(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info) argument
722 si_setup_nir_user_data(struct si_context * sctx,const struct pipe_grid_info * info) argument
765 si_emit_dispatch_packets(struct si_context * sctx,const struct pipe_grid_info * info) argument
852 si_check_needs_implicit_sync(struct si_context * sctx) argument
897 struct si_context *sctx = (struct si_context *)ctx; local in function:si_launch_grid
1046 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_compute_state
1065 si_init_compute_functions(struct si_context * sctx) argument
[all...]
H A Dsi_build_pm4.h64 #define radeon_end_update_context_roll(sctx) do { \
67 (sctx)->context_roll = true; \
156 #define radeon_opt_set_context_reg(sctx, offset, reg, val) do { \
158 if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
159 sctx->tracked_regs.reg_value[reg] != __value) { \
161 sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
162 sctx->tracked_regs.reg_value[reg] = __value; \
172 #define radeon_opt_set_context_reg2(sctx, offset, reg, val1, val2) do { \
174 if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x3) != 0x3 || \
175 sctx
[all...]
H A Dsi_descriptors.c128 static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc) argument
155 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
156 si_optimal_tcc_alignment(sctx, upload_size), &buffer_offset,
166 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
180 si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *desc) argument
185 radeon_add_to_buffer_list(sctx, &sctx
202 si_sampler_and_image_descriptors(struct si_context * sctx,unsigned shader) argument
217 si_sampler_view_add_buffer(struct si_context * sctx,struct pipe_resource * resource,enum radeon_bo_usage usage,bool is_stencil_sampler,bool check_mem) argument
236 si_sampler_views_begin_new_cs(struct si_context * sctx,struct si_samplers * samplers) argument
250 si_sampler_views_check_encrypted(struct si_context * sctx,struct si_samplers * samplers,unsigned samplers_declared) argument
441 si_set_sampler_view_desc(struct si_context * sctx,struct si_sampler_view * sview,struct si_sampler_state * sstate,uint32_t * restrict desc) argument
515 si_set_sampler_views(struct si_context * sctx,unsigned shader,unsigned start_slot,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views,bool disallow_early_out) argument
606 si_update_shader_needs_decompress_mask(struct si_context * sctx,unsigned shader) argument
623 struct si_context *sctx = (struct si_context *)ctx; local in function:si_pipe_set_sampler_views
666 si_image_views_begin_new_cs(struct si_context * sctx,struct si_images * images) argument
681 si_image_views_check_encrypted(struct si_context * sctx,struct si_images * images,unsigned images_declared) argument
911 si_update_ps_colorbuf0_slot(struct si_context * sctx) argument
984 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_sampler_states
1026 si_init_buffer_resources(struct si_context * sctx,struct si_buffer_resources * buffers,struct si_descriptors * descs,unsigned num_buffers,short shader_userdata_rel_index,enum radeon_bo_priority priority,enum radeon_bo_priority priority_constbuf) argument
1070 si_buffer_resources_begin_new_cs(struct si_context * sctx,struct si_buffer_resources * buffers) argument
1086 si_buffer_resources_check_encrypted(struct si_context * sctx,struct si_buffer_resources * buffers) argument
1124 si_vertex_buffers_begin_new_cs(struct si_context * sctx) argument
1150 si_const_and_shader_buffer_descriptors(struct si_context * sctx,unsigned shader) argument
1156 si_upload_const_buffer(struct si_context * sctx,struct si_resource ** buf,const uint8_t * ptr,unsigned size,uint32_t * const_offset) argument
1167 si_set_constant_buffer(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,uint slot,bool take_ownership,const struct pipe_constant_buffer * input) argument
1225 si_invalidate_inlinable_uniforms(struct si_context * sctx,enum pipe_shader_type shader) argument
1242 struct si_context *sctx = (struct si_context *)ctx; local in function:si_pipe_set_constant_buffer
1271 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_inlinable_constants
1293 si_get_pipe_constant_buffer(struct si_context * sctx,uint shader,uint slot,struct pipe_constant_buffer * cbuf) argument
1304 si_set_shader_buffer(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,uint slot,const struct pipe_shader_buffer * sbuffer,bool writable,enum radeon_bo_priority priority) argument
1350 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_shader_buffers
1374 si_get_shader_buffers(struct si_context * sctx,enum pipe_shader_type shader,uint start_slot,uint count,struct pipe_shader_buffer * sbuf) argument
1388 si_set_internal_const_buffer(struct si_context * sctx,uint slot,const struct pipe_constant_buffer * input) argument
1394 si_set_internal_shader_buffer(struct si_context * sctx,uint slot,const struct pipe_shader_buffer * sbuffer) argument
1401 si_set_ring_buffer(struct si_context * sctx,uint slot,struct pipe_resource * buffer,unsigned stride,unsigned num_records,bool add_tid,bool swizzle,unsigned element_size,unsigned index_stride,uint64_t offset) argument
1498 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_polygon_stipple
1514 si_resident_handles_update_needs_color_decompress(struct si_context * sctx) argument
1555 si_update_needs_color_decompress_masks(struct si_context * sctx) argument
1571 si_reset_buffer_resources(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,uint64_t slot_mask,struct pipe_resource * buf,enum radeon_bo_priority priority) argument
1603 si_rebind_buffer(struct si_context * sctx,struct pipe_resource * buf) argument
1797 si_upload_bindless_descriptor(struct si_context * sctx,unsigned desc_slot,unsigned num_dwords) argument
1812 si_upload_bindless_descriptors(struct si_context * sctx) argument
1849 si_update_bindless_texture_descriptor(struct si_context * sctx,struct si_texture_handle * tex_handle) argument
1869 si_update_bindless_image_descriptor(struct si_context * sctx,struct si_image_handle * img_handle) argument
1892 si_update_all_resident_texture_descriptors(struct si_context * sctx) argument
1906 si_update_all_texture_descriptors(struct si_context * sctx) argument
1948 si_mark_shader_pointers_dirty(struct si_context * sctx,unsigned shader) argument
1966 si_shader_pointers_mark_dirty(struct si_context * sctx) argument
1986 si_set_user_data_base(struct si_context * sctx,unsigned shader,uint32_t new_base) argument
2009 si_shader_change_notify(struct si_context * sctx) argument
2075 si_emit_global_shader_pointers(struct si_context * sctx,struct si_descriptors * descs) argument
2111 si_emit_graphics_shader_pointers(struct si_context * sctx) argument
2140 si_emit_compute_shader_pointers(struct si_context * sctx) argument
2200 si_init_bindless_descriptors(struct si_context * sctx,struct si_descriptors * desc,short shader_userdata_rel_index,unsigned num_elements) argument
2221 si_release_bindless_descriptors(struct si_context * sctx) argument
2227 si_get_first_free_bindless_slot(struct si_context * sctx) argument
2248 si_create_bindless_descriptor(struct si_context * sctx,uint32_t * desc_list,unsigned size) argument
2279 si_update_bindless_buffer_descriptor(struct si_context * sctx,unsigned desc_slot,struct pipe_resource * resource,uint64_t offset,bool * desc_dirty) argument
2308 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_texture_handle
2353 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_texture_handle
2374 struct si_context *sctx = (struct si_context *)ctx; local in function:si_make_texture_handle_resident
2441 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_image_handle
2480 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_image_handle
2498 struct si_context *sctx = (struct si_context *)ctx; local in function:si_make_image_handle_resident
2559 si_resident_buffers_add_all_to_bo_list(struct si_context * sctx) argument
2588 si_init_all_descriptors(struct si_context * sctx) argument
2696 si_upload_shader_descriptors(struct si_context * sctx,unsigned mask) argument
2717 si_upload_graphics_shader_descriptors(struct si_context * sctx) argument
2723 si_upload_compute_shader_descriptors(struct si_context * sctx) argument
2733 si_release_all_descriptors(struct si_context * sctx) argument
2756 si_gfx_resources_check_encrypted(struct si_context * sctx) argument
2822 si_gfx_resources_add_all_to_bo_list(struct si_context * sctx) argument
2839 si_compute_resources_check_encrypted(struct si_context * sctx) argument
2854 si_compute_resources_add_all_to_bo_list(struct si_context * sctx) argument
2870 si_add_all_descriptors_to_bo_list(struct si_context * sctx) argument
2881 si_set_active_descriptors(struct si_context * sctx,unsigned desc_idx,uint64_t new_active_mask) argument
2903 si_set_active_descriptors_for_shader(struct si_context * sctx,struct si_shader_selector * sel) argument
[all...]
H A Dsi_compute_blit.c32 static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_coherency coher, argument
35 if ((sctx->chip_class >= GFX9 && (coher == SI_COHERENCY_CB_META ||
38 (sctx->chip_class >= GFX7 && coher == SI_COHERENCY_SHADER))
44 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher, argument
62 void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *info, argument
68 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
71 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
74 sctx->flags |= SI_CONTEXT_PFP_SYNC_ME;
79 sctx->flags |= SI_CONTEXT_INV_VCACHE;
82 sctx
118 si_launch_grid_internal_ssbos(struct si_context * sctx,struct pipe_grid_info * info,void * shader,unsigned flags,enum si_coherency coher,unsigned num_buffers,const struct pipe_shader_buffer * buffers,unsigned writeable_bitmask) argument
163 si_compute_clear_buffer_rmw(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_offset,unsigned size,uint32_t clear_value,uint32_t writebitmask,unsigned flags,enum si_coherency coher) argument
204 si_compute_clear_12bytes_buffer(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_offset,unsigned size,const uint32_t * clear_value,unsigned flags,enum si_coherency coher) argument
239 si_compute_do_clear_or_copy(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_offset,struct pipe_resource * src,unsigned src_offset,unsigned size,const uint32_t * clear_value,unsigned clear_value_size,unsigned flags,enum si_coherency coher) argument
310 si_clear_buffer(struct si_context * sctx,struct pipe_resource * dst,uint64_t offset,uint64_t size,uint32_t * clear_value,uint32_t clear_value_size,unsigned flags,enum si_coherency coher,enum si_clear_method method) argument
397 si_copy_buffer(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,uint64_t dst_offset,uint64_t src_offset,unsigned size,unsigned flags) argument
419 si_compute_copy_image(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_level,struct pipe_resource * src,unsigned src_level,unsigned dstx,unsigned dsty,unsigned dstz,const struct pipe_box * src_box,bool is_dcc_decompress,unsigned flags) argument
601 si_retile_dcc(struct si_context * sctx,struct si_texture * tex) argument
647 gfx9_clear_dcc_msaa(struct si_context * sctx,struct pipe_resource * res,uint32_t clear_value,unsigned flags,enum si_coherency coher) argument
698 struct si_context *sctx = (struct si_context *)ctx; local in function:si_compute_expand_fmask
768 si_init_compute_blit_functions(struct si_context * sctx) argument
779 struct si_context *sctx = (struct si_context *)ctx; local in function:si_compute_clear_render_target
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_streamout.c30 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
44 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_so_target
53 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
81 void si_streamout_buffers_dirty(struct si_context *sctx) argument
83 if (!sctx->streamout.enabled_mask)
86 si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_begin);
87 si_set_streamout_enable(sctx, true);
95 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_streamout_targets
96 unsigned old_num_targets = sctx
192 si_flush_vgt_streamout(struct si_context * sctx) argument
218 si_emit_streamout_begin(struct si_context * sctx) argument
273 si_emit_streamout_end(struct si_context * sctx) argument
321 si_emit_streamout_enable(struct si_context * sctx) argument
335 si_set_streamout_enable(struct si_context * sctx,bool enable) argument
352 si_update_prims_generated_query_state(struct si_context * sctx,unsigned type,int diff) argument
369 si_init_streamout_functions(struct si_context * sctx) argument
[all...]
H A Dsi_state_draw.c69 static void si_emit_derived_tess_state(struct si_context *sctx, argument
73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
76 /* The TES pointer will only be used for sctx->last_tcs.
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx
462 si_init_ia_multi_vgt_param_table(struct si_context * sctx) argument
491 si_get_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_info * info,unsigned num_patches) argument
543 si_emit_rasterizer_prim_state(struct si_context * sctx) argument
569 si_emit_vs_state(struct si_context * sctx,const struct pipe_draw_info * info) argument
604 si_prim_restart_index_changed(struct si_context * sctx,const struct pipe_draw_info * info) argument
612 si_emit_draw_registers(struct si_context * sctx,const struct pipe_draw_info * info,unsigned num_patches) argument
665 si_emit_draw_packets(struct si_context * sctx,const struct pipe_draw_info * info,struct pipe_resource * indexbuf,unsigned index_size,unsigned index_offset) argument
867 si_emit_surface_sync(struct si_context * sctx,unsigned cp_coher_cntl) argument
896 si_emit_cache_flush(struct si_context * sctx) argument
1151 si_get_draw_start_count(struct si_context * sctx,const struct pipe_draw_info * info,unsigned * start,unsigned * count) argument
1217 si_emit_all_states(struct si_context * sctx,const struct pipe_draw_info * info,unsigned skip_atom_mask) argument
1254 struct si_context *sctx = (struct si_context *)ctx; local in function:si_draw_vbo
1585 struct si_context *sctx = (struct si_context*)pipe; local in function:si_draw_rectangle
1621 si_trace_emit(struct si_context * sctx) argument
1636 si_init_draw_functions(struct si_context * sctx) argument
[all...]
H A Dsi_pipe.c149 struct si_context *sctx = (struct si_context *)context; local in function:si_destroy_context
152 util_queue_finish(&sctx->screen->shader_compiler_queue);
153 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
162 si_release_all_descriptors(sctx);
164 pipe_resource_reference(&sctx->esgs_ring, NULL);
165 pipe_resource_reference(&sctx->gsvs_ring, NULL);
166 pipe_resource_reference(&sctx->tess_rings, NULL);
167 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
168 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
169 si_resource_reference(&sctx
278 struct si_context *sctx = (struct si_context *)ctx; local in function:si_get_reset_status
300 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_device_reset_callback
309 si_check_device_reset(struct si_context * sctx) argument
338 struct si_context *sctx = (struct si_context *)ctx; local in function:si_emit_string_marker
349 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_debug_callback
364 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_log_context
388 struct si_context *sctx = CALLOC_STRUCT(si_context); local in function:si_create_context
759 struct si_context *sctx = (struct si_context *)ctx; local in function:si_test_vmfault
788 si_test_gds_memory_management(struct si_context * sctx,unsigned alloc_size,unsigned alignment,enum radeon_bo_domain domain) argument
[all...]
H A Dsi_cp_dma.c42 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx) argument
44 unsigned max = sctx->chip_class >= GFX9 ?
57 static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, argument
63 assert(size <= cp_dma_max_byte_count(sctx));
64 assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
66 if (sctx->chip_class >= GFX9)
75 if (sctx->chip_class >= GFX9)
85 if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
93 } else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
105 } else if (sctx
140 si_cp_dma_wait_for_idle(struct si_context * sctx) argument
151 si_cp_dma_prepare(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,unsigned byte_count,uint64_t remaining_size,unsigned user_flags,enum si_coherency coher,bool * is_first,unsigned * packet_flags) argument
210 si_cp_dma_clear_buffer(struct si_context * sctx,struct radeon_cmdbuf * cs,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy) argument
262 si_cp_dma_realign_engine(struct si_context * sctx,unsigned size,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy,bool * is_first) argument
305 si_cp_dma_copy_buffer(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,uint64_t dst_offset,uint64_t src_offset,unsigned size,unsigned user_flags,enum si_coherency coher,enum si_cache_policy cache_policy) argument
412 cik_prefetch_TC_L2_async(struct si_context * sctx,struct pipe_resource * buf,uint64_t offset,unsigned size) argument
421 cik_prefetch_shader_async(struct si_context * sctx,struct si_pm4_state * state) argument
430 cik_prefetch_VBO_descriptors(struct si_context * sctx) argument
446 cik_emit_prefetch_L2(struct si_context * sctx,bool vertex_stage_only) argument
549 si_test_gds(struct si_context * sctx) argument
585 si_cp_write_data(struct si_context * sctx,struct si_resource * buf,unsigned offset,unsigned size,unsigned dst_sel,unsigned engine,const void * data) argument
610 si_cp_copy_data(struct si_context * sctx,unsigned dst_sel,struct si_resource * dst,unsigned dst_offset,unsigned src_sel,struct si_resource * src,unsigned src_offset) argument
[all...]
H A Dsi_descriptors.c141 static bool si_upload_descriptors(struct si_context *sctx, argument
165 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
171 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
172 si_optimal_tcc_alignment(sctx, upload_size),
184 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer,
192 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
193 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
195 si_mark_atom_dirty(sctx,
200 si_descriptors_begin_new_cs(struct si_context * sctx,struct si_descriptors * desc) argument
231 si_sampler_and_image_descriptors(struct si_context * sctx,unsigned shader) argument
245 si_sampler_view_add_buffer(struct si_context * sctx,struct pipe_resource * resource,enum radeon_bo_usage usage,bool is_stencil_sampler,bool check_mem) argument
276 si_sampler_views_begin_new_cs(struct si_context * sctx,struct si_samplers * samplers) argument
427 si_set_sampler_view_desc(struct si_context * sctx,struct si_sampler_view * sview,struct si_sampler_state * sstate,uint32_t * desc) argument
494 si_set_sampler_view(struct si_context * sctx,unsigned shader,unsigned slot,struct pipe_sampler_view * view,bool disallow_early_out) argument
561 si_update_shader_needs_decompress_mask(struct si_context * sctx,unsigned shader) argument
580 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_sampler_views
633 si_image_views_begin_new_cs(struct si_context * sctx,struct si_images * images) argument
869 si_update_ps_colorbuf0_slot(struct si_context * sctx) argument
946 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_sampler_states
1020 si_buffer_resources_begin_new_cs(struct si_context * sctx,struct si_buffer_resources * buffers) argument
1061 si_vertex_buffers_begin_new_cs(struct si_context * sctx) argument
1086 si_upload_vertex_buffer_descriptors(struct si_context * sctx) argument
1188 si_const_and_shader_buffer_descriptors(struct si_context * sctx,unsigned shader) argument
1193 si_upload_const_buffer(struct si_context * sctx,struct si_resource ** buf,const uint8_t * ptr,unsigned size,uint32_t * const_offset) argument
1206 si_set_constant_buffer(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,uint slot,const struct pipe_constant_buffer * input) argument
1276 struct si_context *sctx = (struct si_context *)ctx; local in function:si_pipe_set_constant_buffer
1296 si_get_pipe_constant_buffer(struct si_context * sctx,uint shader,uint slot,struct pipe_constant_buffer * cbuf) argument
1309 si_set_shader_buffer(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,uint slot,const struct pipe_shader_buffer * sbuffer,bool writable,enum radeon_bo_priority priority) argument
1365 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_shader_buffers
1385 si_get_shader_buffers(struct si_context * sctx,enum pipe_shader_type shader,uint start_slot,uint count,struct pipe_shader_buffer * sbuf) argument
1404 si_set_rw_buffer(struct si_context * sctx,uint slot,const struct pipe_constant_buffer * input) argument
1411 si_set_rw_shader_buffer(struct si_context * sctx,uint slot,const struct pipe_shader_buffer * sbuffer) argument
1418 si_set_ring_buffer(struct si_context * sctx,uint slot,struct pipe_resource * buffer,unsigned stride,unsigned num_records,bool add_tid,bool swizzle,unsigned element_size,unsigned index_stride,uint64_t offset) argument
1517 struct si_context *sctx = (struct si_context *)ctx; local in function:si_set_polygon_stipple
1534 si_resident_handles_update_needs_color_decompress(struct si_context * sctx) argument
1577 si_update_needs_color_decompress_masks(struct si_context * sctx) argument
1593 si_reset_buffer_resources(struct si_context * sctx,struct si_buffer_resources * buffers,unsigned descriptors_idx,unsigned slot_mask,struct pipe_resource * buf,enum radeon_bo_priority priority) argument
1628 si_rebind_buffer(struct si_context * sctx,struct pipe_resource * buf) argument
1848 si_upload_bindless_descriptor(struct si_context * sctx,unsigned desc_slot,unsigned num_dwords) argument
1864 si_upload_bindless_descriptors(struct si_context * sctx) argument
1906 si_update_bindless_texture_descriptor(struct si_context * sctx,struct si_texture_handle * tex_handle) argument
1928 si_update_bindless_image_descriptor(struct si_context * sctx,struct si_image_handle * img_handle) argument
1951 si_update_all_resident_texture_descriptors(struct si_context * sctx) argument
1967 si_update_all_texture_descriptors(struct si_context * sctx) argument
2013 si_mark_shader_pointers_dirty(struct si_context * sctx,unsigned shader) argument
2026 si_shader_pointers_begin_new_cs(struct si_context * sctx) argument
2038 si_set_user_data_base(struct si_context * sctx,unsigned shader,uint32_t new_base) argument
2063 si_shader_change_notify(struct si_context * sctx) argument
2112 si_emit_shader_pointer(struct si_context * sctx,struct si_descriptors * desc,unsigned sh_base) argument
2123 si_emit_consecutive_shader_pointers(struct si_context * sctx,unsigned pointer_mask,unsigned sh_base) argument
2147 si_emit_global_shader_pointers(struct si_context * sctx,struct si_descriptors * descs) argument
2171 si_emit_graphics_shader_pointers(struct si_context * sctx) argument
2223 si_emit_compute_shader_pointers(struct si_context * sctx) argument
2239 si_init_bindless_descriptors(struct si_context * sctx,struct si_descriptors * desc,short shader_userdata_rel_index,unsigned num_elements) argument
2263 si_release_bindless_descriptors(struct si_context * sctx) argument
2269 si_get_first_free_bindless_slot(struct si_context * sctx) argument
2291 si_create_bindless_descriptor(struct si_context * sctx,uint32_t * desc_list,unsigned size) argument
2321 si_update_bindless_buffer_descriptor(struct si_context * sctx,unsigned desc_slot,struct pipe_resource * resource,uint64_t offset,bool * desc_dirty) argument
2353 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_texture_handle
2401 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_texture_handle
2423 struct si_context *sctx = (struct si_context *)ctx; local in function:si_make_texture_handle_resident
2505 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_image_handle
2547 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_image_handle
2567 struct si_context *sctx = (struct si_context *)ctx; local in function:si_make_image_handle_resident
2639 si_resident_buffers_add_all_to_bo_list(struct si_context * sctx) argument
2677 si_init_all_descriptors(struct si_context * sctx) argument
2787 si_upload_shader_descriptors(struct si_context * sctx,unsigned mask) argument
2808 si_upload_graphics_shader_descriptors(struct si_context * sctx) argument
2814 si_upload_compute_shader_descriptors(struct si_context * sctx) argument
2824 si_release_all_descriptors(struct si_context * sctx) argument
2848 si_gfx_resources_add_all_to_bo_list(struct si_context * sctx) argument
2865 si_compute_resources_add_all_to_bo_list(struct si_context * sctx) argument
2881 si_all_descriptors_begin_new_cs(struct si_context * sctx) argument
2894 si_set_active_descriptors(struct si_context * sctx,unsigned desc_idx,uint64_t new_active_mask) argument
2918 si_set_active_descriptors_for_shader(struct si_context * sctx,struct si_shader_selector * sel) argument
[all...]
H A Dsi_state_binning.c66 static struct uvec2 si_get_color_bin_size(struct si_context *sctx, argument
69 unsigned num_fragments = sctx->framebuffer.nr_color_samples;
73 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
78 (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
84 if (si_get_ps_iter_samples(sctx) >= 2)
179 return si_find_bin_size(sctx->screen, table, sum);
182 static struct uvec2 si_get_depth_bin_size(struct si_context *sctx) argument
184 struct si_state_dsa *dsa = sctx->queued.named.dsa;
186 if (!sctx->framebuffer.state.zsbuf ||
194 (struct si_texture*)sctx
311 si_emit_dpbb_disable(struct si_context * sctx) argument
327 si_emit_dpbb_state(struct si_context * sctx) argument
[all...]
H A Dsi_compute.c202 struct si_context *sctx = (struct si_context *)ctx; local in function:si_create_compute_state
226 program->compiler_ctx_state.debug = sctx->debug;
227 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
230 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
255 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
257 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
269 struct si_context *sctx = (struct si_context*)ctx; local in function:si_bind_compute_state
272 sctx->cs_shader_state.program = program;
280 si_set_active_descriptors(sctx,
296 struct si_context *sctx = (struct si_context*)ctx; local in function:si_set_global_binding
320 si_initialize_compute(struct si_context * sctx) argument
371 si_setup_compute_scratch_buffer(struct si_context * sctx,struct si_shader * shader,struct si_shader_config * config) argument
409 si_switch_compute_shader(struct si_context * sctx,struct si_compute * program,struct si_shader * shader,const amd_kernel_code_t * code_object,unsigned offset) argument
519 setup_scratch_rsrc_user_sgprs(struct si_context * sctx,const amd_kernel_code_t * code_object,unsigned user_sgpr) argument
562 si_setup_user_sgprs_co_v2(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info,uint64_t kernel_args_va) argument
653 si_upload_compute_input(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info) argument
717 si_setup_tgsi_user_data(struct si_context * sctx,const struct pipe_grid_info * info) argument
760 si_emit_dispatch_packets(struct si_context * sctx,const struct pipe_grid_info * info) argument
859 struct si_context *sctx = (struct si_context*)ctx; local in function:si_launch_grid
983 struct si_context *sctx = (struct si_context*)ctx; local in function:si_delete_compute_state
1001 si_init_compute_functions(struct si_context * sctx) argument
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H A Dsi_compute_blit.c33 static enum si_cache_policy get_cache_policy(struct si_context *sctx, argument
37 if ((sctx->chip_class >= GFX9 && (coher == SI_COHERENCY_CB_META ||
39 (sctx->chip_class >= CIK && coher == SI_COHERENCY_SHADER))
45 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher, argument
62 static void si_compute_internal_begin(struct si_context *sctx) argument
64 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
65 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
66 sctx->render_cond_force_off = true;
69 static void si_compute_internal_end(struct si_context *sctx) argument
71 sctx
76 si_compute_do_clear_or_copy(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_offset,struct pipe_resource * src,unsigned src_offset,unsigned size,const uint32_t * clear_value,unsigned clear_value_size,enum si_coherency coher) argument
187 si_clear_buffer(struct si_context * sctx,struct pipe_resource * dst,uint64_t offset,uint64_t size,uint32_t * clear_value,uint32_t clear_value_size,enum si_coherency coher,bool force_cpdma) argument
292 si_copy_buffer(struct si_context * sctx,struct pipe_resource * dst,struct pipe_resource * src,uint64_t dst_offset,uint64_t src_offset,unsigned size) argument
316 si_compute_copy_image(struct si_context * sctx,struct pipe_resource * dst,unsigned dst_level,struct pipe_resource * src,unsigned src_level,unsigned dstx,unsigned dsty,unsigned dstz,const struct pipe_box * src_box) argument
429 si_retile_dcc(struct si_context * sctx,struct si_texture * tex) argument
507 si_init_compute_blit_functions(struct si_context * sctx) argument
520 struct si_context *sctx = (struct si_context *)ctx; local in function:si_compute_clear_render_target
[all...]
H A Dsi_state_shaders.c556 static void si_emit_shader_es(struct si_context *sctx) argument
558 struct si_shader *shader = sctx->queued.named.es->shader;
559 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
564 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
574 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
578 if (initial_cdw != sctx->gfx_cs->current.cdw)
579 sctx->context_roll = true;
761 static void si_emit_shader_gs(struct si_context *sctx) argument
763 struct si_shader *shader = sctx
961 si_emit_shader_vs(struct si_context * sctx) argument
1165 si_emit_shader_ps(struct si_context * sctx) argument
1364 si_get_alpha_test_func(struct si_context * sctx) argument
1373 si_shader_selector_key_vs(struct si_context * sctx,struct si_shader_selector * vs,struct si_shader_key * key,struct si_vs_prolog_bits * prolog_key) argument
1397 si_shader_selector_key_hw_vs(struct si_context * sctx,struct si_shader_selector * vs,struct si_shader_key * key) argument
1451 struct si_context *sctx = (struct si_context *)ctx; local in function:si_shader_selector_key
1990 struct si_context *sctx = (struct si_context *)ctx; local in function:si_shader_select
2163 si_schedule_initial_compile(struct si_context * sctx,unsigned processor,struct util_queue_fence * ready_fence,struct si_compiler_ctx_state * compiler_ctx_state,void * job,util_queue_execute_func execute) argument
2222 struct si_context *sctx = (struct si_context*)ctx; local in function:si_create_shader_selector
2475 si_update_streamout_state(struct si_context * sctx) argument
2487 si_update_clip_regs(struct si_context * sctx,struct si_shader_selector * old_hw_vs,struct si_shader * old_hw_vs_variant,struct si_shader_selector * next_hw_vs,struct si_shader * next_hw_vs_variant) argument
2507 si_update_common_shader_state(struct si_context * sctx) argument
2526 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_vs_shader
2546 si_update_tess_uses_prim_id(struct si_context * sctx) argument
2561 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_gs_shader
2591 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_tcs_shader
2612 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_tes_shader
2642 struct si_context *sctx = (struct si_context *)ctx; local in function:si_bind_ps_shader
2673 si_delete_shader(struct si_context * sctx,struct si_shader * shader) argument
2723 si_destroy_shader_selector(struct si_context * sctx,struct si_shader_selector * sel) argument
2766 struct si_context *sctx = (struct si_context *)ctx; local in function:si_delete_shader_selector
2772 si_get_ps_input_cntl(struct si_context * sctx,struct si_shader * vs,unsigned name,unsigned index,unsigned interpolate) argument
2830 si_emit_spi_map(struct si_context * sctx) argument
2887 si_init_config_add_vgt_flush(struct si_context * sctx) argument
2906 si_update_gs_ring_buffers(struct si_context * sctx) argument
3057 si_update_scratch_buffer(struct si_context * sctx,struct si_shader * shader) argument
3112 si_get_tcs_current(struct si_context * sctx) argument
3121 si_update_scratch_relocs(struct si_context * sctx) argument
3176 si_update_spi_tmpring_size(struct si_context * sctx) argument
3245 si_init_tess_factor_ring(struct si_context * sctx) argument
3297 si_update_vgt_shader_config(struct si_context * sctx) argument
3333 si_update_shaders(struct si_context * sctx) argument
3540 si_emit_scratch_state(struct si_context * sctx) argument
3554 si_init_shader_functions(struct si_context * sctx) argument
[all...]
H A Dsi_build_pm4.h120 static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset, argument
123 struct radeon_cmdbuf *cs = sctx->gfx_cs;
125 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
126 sctx->tracked_regs.reg_value[reg] != value) {
129 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
130 sctx->tracked_regs.reg_value[reg] = value;
140 static inline void radeon_opt_set_context_reg2(struct si_context *sctx, unsigned offset, argument
144 struct radeon_cmdbuf *cs = sctx->gfx_cs;
146 if (((sctx->tracked_regs.reg_saved >> reg) & 0x3) != 0x3 ||
147 sctx
162 radeon_opt_set_context_reg3(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value1,unsigned value2,unsigned value3) argument
187 radeon_opt_set_context_reg4(struct si_context * sctx,unsigned offset,enum si_tracked_reg reg,unsigned value1,unsigned value2,unsigned value3,unsigned value4) argument
216 radeon_opt_set_context_regn(struct si_context * sctx,unsigned offset,unsigned * value,unsigned * saved_val,unsigned num) argument
[all...]
H A Dsi_blit.c45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op) argument
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx
89 si_blitter_end(struct si_context * sctx) argument
111 si_blit_dbcb_copy(struct si_context * sctx,struct si_texture * src,struct si_texture * dst,unsigned planes,unsigned level_mask,unsigned first_layer,unsigned last_layer,unsigned first_sample,unsigned last_sample) argument
211 si_blit_decompress_zs_planes_in_place(struct si_context * sctx,struct si_texture * texture,unsigned planes,unsigned level_mask,unsigned first_layer,unsigned last_layer) argument
280 si_blit_decompress_zs_in_place(struct si_context * sctx,struct si_texture * texture,unsigned levels_z,unsigned levels_s,unsigned first_layer,unsigned last_layer) argument
314 si_decompress_depth(struct si_context * sctx,struct si_texture * tex,unsigned required_planes,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
428 si_decompress_sampler_depth_textures(struct si_context * sctx,struct si_samplers * textures) argument
455 si_blit_decompress_color(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,bool need_dcc_decompress) argument
542 si_decompress_color_texture(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level) argument
555 si_decompress_sampler_color_textures(struct si_context * sctx,struct si_samplers * textures) argument
578 si_decompress_image_color_textures(struct si_context * sctx,struct si_images * images) argument
600 si_check_render_feedback_texture(struct si_context * sctx,struct si_texture * tex,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
634 si_check_render_feedback_textures(struct si_context * sctx,struct si_samplers * textures) argument
659 si_check_render_feedback_images(struct si_context * sctx,struct si_images * images) argument
684 si_check_render_feedback_resident_textures(struct si_context * sctx) argument
705 si_check_render_feedback_resident_images(struct si_context * sctx) argument
726 si_check_render_feedback(struct si_context * sctx) argument
748 si_decompress_resident_textures(struct si_context * sctx) argument
772 si_decompress_resident_images(struct si_context * sctx) argument
784 si_decompress_textures(struct si_context * sctx,unsigned shader_mask) argument
846 struct si_context *sctx = (struct si_context *)ctx; local in function:si_decompress_subresource
904 struct si_context *sctx = (struct si_context *)ctx; local in function:si_resource_copy_region
1062 si_do_CB_resolve(struct si_context * sctx,const struct pipe_blit_info * info,struct pipe_resource * dst,unsigned dst_level,unsigned dst_z,enum pipe_format format) argument
1086 struct si_context *sctx = (struct si_context*)ctx; local in function:do_hardware_msaa_resolve
1218 struct si_context *sctx = (struct si_context*)ctx; local in function:si_blit
1273 struct si_context *sctx = (struct si_context*)ctx; local in function:si_generate_mipmap
1306 struct si_context *sctx = (struct si_context*)ctx; local in function:si_flush_resource
1357 si_decompress_dcc(struct si_context * sctx,struct si_texture * tex) argument
1370 si_init_blit_functions(struct si_context * sctx) argument
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