Searched refs:sgpr (Results 1 - 25 of 30) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_live_var_analysis.cpp105 new_demand.sgpr -= phi_info[block->index].logical_phi_sgpr_ops;
114 register_demand[idx] = RegisterDemand(new_demand.vgpr, new_demand.sgpr);
138 new_demand.sgpr += phi_info[block->index].logical_phi_sgpr_ops;
203 assert(definition.getTemp().type() == RegType::sgpr);
249 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) {
252 assert(operand.getTemp().type() == RegType::sgpr);
365 if (new_demand.vgpr > vgpr_limit || new_demand.sgpr > sgpr_limit) {
369 program->num_waves = program->dev.physical_sgprs / get_sgpr_alloc(program, new_demand.sgpr);
410 program->max_reg_demand.sgpr = get_addr_sgpr_from_waves(program, program->num_waves);
437 result.register_demand[block.index].back().sgpr
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H A Daco_validate.cpp313 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
321 unsigned sgpr[] = {0, 0}; local in function:aco::validate_ir
327 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
339 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
350 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
355 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
359 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
361 sgpr[num_sgprs++] = op.tempId();
374 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
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H A Daco_spill.cpp472 reg_pressure.sgpr =
473 std::max<int16_t>(reg_pressure.sgpr, ctx.register_demand[pred].back().sgpr);
528 type = RegType::sgpr;
530 if (type == RegType::sgpr && loop_demand.sgpr <= ctx.target_pressure.sgpr)
539 (ctx.remat.count(pair.first) && type == RegType::sgpr)) &&
548 if (type == RegType::sgpr)
550 type = RegType::sgpr;
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H A Daco_ir.h302 sgpr, enumerator in enum:aco::RegType
346 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; }
358 if (type == RegType::sgpr) {
1807 constexpr RegisterDemand(const int16_t v, const int16_t s) noexcept : vgpr{v}, sgpr{s} {}
1809 int16_t sgpr = 0; member in struct:aco::RegisterDemand
1813 return a.vgpr == b.vgpr && a.sgpr == b.sgpr;
1818 return vgpr > other.vgpr || sgpr > other.sgpr;
1823 if (t.type() == RegType::sgpr)
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H A Daco_instruction_selection_setup.cpp244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components);
465 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
567 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
575 RegType type = RegType::sgpr;
611 case nir_intrinsic_load_viewport_y_offset: type = RegType::sgpr; break;
728 type = nir_dest_is_divergent(intrinsic->dest) ? RegType::vgpr : RegType::sgpr;
731 type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr;
748 RegType type = nir_dest_is_divergent(tex->dest) ? RegType::vgpr : RegType::sgpr;
768 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
774 RegType type = RegType::sgpr;
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H A Daco_optimizer.cpp67 * propagates sgpr's on VALU instructions.
530 if (temp.type() == RegType::sgpr && !can_accept_sgpr)
534 if (temp.type() == RegType::sgpr && !can_accept_sgpr)
667 unsigned sgpr[] = {0, 0}; local in function:aco::check_vop3_operands
672 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
674 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
676 sgpr[num_sgprs++] = op.tempId();
900 op.getTemp().type() == RegType::sgpr)) {
1019 if (info.is_temp() && info.temp.type() == RegType::sgpr
2753 Temp sgpr = info.is_extract() ? info.instr->operands[0].getTemp() : info.temp; local in function:aco::apply_sgprs
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H A Daco_insert_NOPs.cpp412 if (def.regClass().type() != RegType::sgpr) {
443 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr)
504 if (def.regClass().type() == RegType::sgpr) {
612 { return def.getTemp().type() == RegType::sgpr; });
H A Daco_register_allocation.cpp189 return {PhysReg{0}, (unsigned)program->max_reg_demand.sgpr};
397 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr);
1318 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0)
1325 bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win);
1349 ctx.program->max_reg_demand.sgpr));
1350 } else if (type == RegType::sgpr && ctx.program->max_reg_demand.sgpr < ctx.sgpr_limit) {
1352 ctx.program->max_reg_demand.sgpr + 1));
1821 for (; reg < ctx.program->max_reg_demand.sgpr && reg_file[PhysReg{(unsigned)reg}]; reg++)
1823 if (reg == ctx.program->max_reg_demand.sgpr) {
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H A Daco_instruction_selection.cpp270 if (val.type() == RegType::sgpr) {
354 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
381 if (vec_src.type() == RegType::sgpr) {
415 if (dst.type() == RegType::sgpr)
433 if (dst.type() == RegType::sgpr)
554 /* if dst is sgpr - split the src, but move the original to sgpr. */
555 vec = bld.pseudo(aco_opcode::p_as_uniform, bld.def(RegClass(RegType::sgpr, vec.size())), vec);
612 if (dst_bits % 32 == 0 || src.type() == RegType::sgpr)
618 assert(src.type() == RegType::sgpr || src_bit
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H A Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) {
500 emit_copies_block(bld, ltg, RegType::sgpr);
H A Daco_print_ir.cpp94 } else if (rc.type() == RegType::sgpr) {
825 fprintf(output, "\tdemand: %u vgpr, %u sgpr\n", demand.vgpr, demand.sgpr);
833 fprintf(output, "(%3u vgpr, %3u sgpr) ", demand.vgpr, demand.sgpr);
H A Daco_ir.cpp284 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
680 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr))
H A Daco_lower_to_hw_instr.cpp433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size));
492 /* p_exclusive_scan needs it to be a sgpr or inline constant for the v_writelane_b32
827 if (dst.regClass().type() == RegType::sgpr) {
1295 /* we need to swap scc and another sgpr */
1529 it->second.op.regClass().type() == RegType::sgpr ? s2 : v2);
1531 it->second.def.regClass().type() == RegType::sgpr ? s2 : v2);
1767 if (preserve_scc && it->second.def.getTemp().type() == RegType::sgpr)
2072 instr->operands[0].regClass().type() == RegType::sgpr) {
2079 assert(instr->definitions[0].regClass().type() == RegType::sgpr);
H A Daco_lower_phis.cpp325 assert(phi_src.regClass().type() == RegType::sgpr);
H A Daco_optimizer_postRA.cpp91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255);
H A Daco_statistics.cpp43 program->statistics[statistic_sgpr_presched] = presched_demand.sgpr;
H A DREADME.md279 Typical issues might be a wrong instruction format leading to a wrong opcode or an sgpr used for vgpr field.
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.3.4.rst179 - aco: fix target calculation when vgpr spilling introduces sgpr
H A D17.3.4.rst95 - ac/nir: account for view index in the user sgpr allocation.
H A D20.1.0.rst1248 - aco: use v_subrev_f32 for fsub with an sgpr operand in src1
3564 - aco: implement 64-bit sgpr swaps
3610 - aco: fix vgpr nir_op_vecn with sgpr operands
3823 - aco: fix creating v_madak if v_mad_f32 has two sgpr literals
H A D20.0.0.rst2887 - aco: fix target calculation when vgpr spilling introduces sgpr
3247 - aco: fix creating v_madak if v_mad_f32 has two sgpr literals
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dhelpers.cpp119 RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0');
H A Dtest_sdwa.cpp334 BEGIN_TEST(optimize.sdwa.extract.sgpr)
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_llvm_build.h178 void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr);
H A Dac_llvm_build.c404 void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr) argument
410 const char *constraint = sgpr ? "=s,0" : "=v,0";

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