Searched refs:sh_base (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h276 #define radeon_emit_one_32bit_pointer(sctx, desc, sh_base) do { \
277 unsigned sh_offset = (sh_base) + (desc)->shader_userdata_offset; \
H A Dsi_descriptors.c1988 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
2056 #define si_emit_consecutive_shader_pointers(sctx, pointer_mask, sh_base) do { \
2057 unsigned sh_reg_base = (sh_base); \
2113 uint32_t *sh_base = sctx->shader_pointers.sh_base; local in function:si_emit_graphics_shader_pointers
2121 sh_base[PIPE_SHADER_VERTEX]);
2123 sh_base[PIPE_SHADER_TESS_EVAL]);
2125 sh_base[PIPE_SHADER_FRAGMENT]);
2127 sh_base[PIPE_SHADER_TESS_CTRL]);
2129 sh_base[PIPE_SHADER_GEOMETR
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H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
1401 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
1770 unsigned sh_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG, local in function:si_upload_and_prefetch_VB_descriptors
1817 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_vb_sgprs);
1889 radeon_set_sh_reg(sh_base + sh_dw_offset * 4,
1901 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs);
H A Dsi_state.h249 uint32_t sh_base[SI_NUM_SHADERS]; member in struct:si_shader_data
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c2041 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
2114 unsigned sh_base)
2117 unsigned sh_offset = sh_base + desc->shader_userdata_offset;
2125 unsigned sh_base)
2127 if (!sh_base)
2138 unsigned sh_offset = sh_base + descs->shader_userdata_offset;
2173 uint32_t *sh_base = sctx->shader_pointers.sh_base; local in function:si_emit_graphics_shader_pointers
2181 sh_base[PIPE_SHADER_VERTEX]);
2183 sh_base[PIPE_SHADER_TESS_EVA
2112 si_emit_shader_pointer(struct si_context * sctx,struct si_descriptors * desc,unsigned sh_base) argument
2123 si_emit_consecutive_shader_pointers(struct si_context * sctx,unsigned pointer_mask,unsigned sh_base) argument
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H A Dsi_state_draw.c83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
586 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
673 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
H A Dsi_state.h232 uint32_t sh_base[SI_NUM_SHADERS]; member in struct:si_shader_data
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c610 uint32_t sh_base = pipeline->user_data_0[stage]; local in function:radv_emit_descriptor_pointers
623 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c809 uint32_t sh_base = pipeline->user_data_0[stage]; local in function:radv_emit_descriptor_pointers
821 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.0.rst3289 - radeonsi: evaluate sh_base in si_emit_vs_state at compile time

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