Searched refs:size_z (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/
H A Dpan_encoder.h160 unsigned size_x, unsigned size_y, unsigned size_z,
166 unsigned values[6] = { size_x, size_y, size_z, num_x, num_y, num_z };
157 panfrost_pack_work_groups_compute(struct mali_invocation_packed * out,unsigned num_x,unsigned num_y,unsigned num_z,unsigned size_x,unsigned size_y,unsigned size_z,bool quirk_graphics,bool indirect_dispatch) argument
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_nir_lower_cs_intrinsics.c220 nir_ssa_def *size_z = nir_channel(b, size_xyz, 2); local in function:lower_cs_intrinsics_convert_block
221 size = nir_imul(b, nir_imul(b, size_x, size_y), size_z);
/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/genxml/
H A Ddecode.c475 unsigned size_z = bits(invocation.invocations, invocation.size_z_shift, invocation.workgroups_x_shift) + 1; local in function:pandecode_invocation
482 size_x, size_y, size_z,
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c3663 struct gen_mi_value size_z = gen_mi_mem32(anv_address_add(addr, 8)); local in function:genX
3667 gen_mi_store(&b, gen_mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
3688 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_z);
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c5057 struct mi_value size_z = mi_mem32(anv_address_add(addr, 8)); local in function:genX
5061 mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z);
5082 mi_store(&b, mi_reg32(MI_PREDICATE_SRC0), size_z);

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