Searched refs:spilling (Results 1 - 25 of 35) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.0.5.rst73 - intel/fs: Use regs_written() in spilling cost heuristic for improved
75 - intel/fs: Take into account amount of data read in spilling cost
H A D10.5.8.rst39 Register spilling clobbers registers used elsewhere in the shader
H A D20.1.8.rst75 - pan/mdg: Fix spilling of non-32-bit types
H A D9.1.5.rst79 - ra: Fix register spilling.
H A D19.3.4.rst179 - aco: fix target calculation when vgpr spilling introduces sgpr
180 spilling
H A D11.0.7.rst117 - nv50/ir: fix (un)spilling of 3-wide results
H A D11.1.2.rst117 - nv50/ir: fix memory corruption when spilling and redoing RA
H A D21.1.4.rst92 - pan/mdg: Fill from TLS before spilling non-SSA nodes
H A D8.0.1.rst106 - i965/fs: Enable register spilling on gen7 too.
H A D21.1.1.rst75 - aco: fix additional register requirements for spilling
H A D21.2.2.rst190 - broadcom/compiler: force a last thrsw for spilling
H A D9.0.2.rst192 - i965/vs: Implement register spilling.
H A D11.0.0.rst124 Register spilling clobbers registers used elsewhere in the shader
H A D20.3.5.rst87 - radv: Improve spilling on discrete GPUs.
H A D10.6.0.rst327 Register spilling clobbers registers used elsewhere in the shader
H A D19.3.0.rst392 - pan/midgard: Fix memory corruption in register spilling
769 - lima/gpir: Fix 64-bit shift in scheduler spilling
813 spilling
817 - aco: simplify calculation of target register pressure when spilling
821 - aco: implement VGPR spilling
824 - aco: only use single-dword loads/stores for spilling
1288 - lima/ppir: optimizations in regalloc spilling code
2886 - freedreno/ir3: fix addr/pred spilling
H A D20.0.0.rst273 - pan/lcra: Use Chaitin's spilling heuristic
313 - pan/midgard: Move spilling code out of scheduler
314 - pan/midgard: Split spill node selection/spilling
716 - aco: only use single-dword loads/stores for spilling
2887 - aco: fix target calculation when vgpr spilling introduces sgpr
2888 spilling
H A D19.1.0.rst1400 - v3d: Dump the VIR after register spilling if we were forced to.
1401 - v3d: Rematerialize MOVs of uniforms instead of spilling them.
1408 - v3d: Fix temporary leaks of temp_registers and when spilling.
1409 - v3d: Do uniform rematerialization spilling before dropping
1493 - v3d: Fix detection of TMU write sequences in register spilling.
2240 - anv/pipeline: Add skeleton support for spilling to bindless
4512 - st/glsl: start spilling out common st glsl conversion code
H A D21.1.0.rst405 - pan/bi: Implement spilling at the clause-level
655 - panfrost: Fix infinite loop spilling
673 - pan/bi: Allow spilling with multiple destinations
933 - radv: Improve spilling on discrete GPUs.
2287 - broadcom/compiler: prepare TMU spilling code to account for TMU pipelining
2293 - broadcom/compiler: disallow spilling if TMU pipelining was enabled
2294 - broadcom/compiler: log spilling shaders to perf output
2316 - broadcom/compiler: use a helper function to decide on TMU spilling
2431 - pan/mdg: Fix spilling when scratch memory is used
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_spill.c121 /* When spilling, we need to reserve a register to serve as the zero'd
136 bool spilling; member in struct:ra_spill_ctx
258 * prioritized for spilling, as per the paper. This just needs to be
396 if (ctx->spilling) {
403 if (ctx->spilling) {
423 if (ctx->spilling) {
429 if (ctx->spilling) {
485 if (ctx->spilling)
661 /* If spilling an immed/const pcopy src, we need to actually materialize it
670 d("spilling ssa
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/xsrc/external/mit/MesaLib/dist/docs/
H A Denvvars.rst313 force spilling of all registers in the scalar backend (useful to
314 debug spilling code)
316 force spilling of all registers in the vec4 backend (useful to
317 debug spilling code)
/xsrc/external/mit/MesaLib/dist/docs/drivers/
H A Dlima.rst100 force spilling of variables in ppir (used for development purposes)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/
H A Dir3-notes.rst379 point we will have to deal with spilling.
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md76 This information is used for spilling and scheduling before register allocation.
/xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/
H A Dir3-notes.rst350 point we will have to deal with spilling.

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