Searched refs:stencil_write_mask (Results 1 - 25 of 39) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Dgen8_cmd_buffer.c358 (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front ||
359 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) &&
458 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
461 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
464 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
506 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
509 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
515 (d->stencil_write_mask.front || d->stencil_write_mask
[all...]
H A Dgen7_cmd_buffer.c230 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
233 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
236 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
H A Danv_cmd_buffer.c67 .stencil_write_mask = {
110 dest->stencil_write_mask = src->stencil_write_mask;
495 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
497 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
H A Danv_pipeline.c1514 dynamic->stencil_write_mask.front =
1516 dynamic->stencil_write_mask.back =
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c394 (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front ||
395 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) &&
552 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
555 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
558 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
618 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
621 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
627 (d->stencil_write_mask.front || d->stencil_write_mask
[all...]
H A Dgfx7_cmd_buffer.c308 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
311 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
314 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
H A Danv_cmd_buffer.c67 .stencil_write_mask = {
164 ANV_CMP_COPY(stencil_write_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
165 ANV_CMP_COPY(stencil_write_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
747 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
749 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c1222 .stencil_write_mask =
1309 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1310 sizeof(src->stencil_write_mask))) {
1311 dest->stencil_write_mask = src->stencil_write_mask;
1862 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1864 cmd->state.dynamic.stencil_write_mask.back = writeMask;
2153 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2154 dynamic->stencil_write_mask
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_structs.h587 unsigned int stencil_write_mask:8; member in struct:brw_cc_unit_state::__anon375735ed2908
1582 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon375735ed7708
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_structs.h587 unsigned int stencil_write_mask:8; member in struct:brw_cc_unit_state::__anon5c4f4f862908
1582 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon5c4f4f867708
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_structs.h587 unsigned int stencil_write_mask:8; member in struct:brw_cc_unit_state::__anon4ebdd7212908
1582 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon4ebdd7217708
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_structs.h587 unsigned int stencil_write_mask:8; member in struct:brw_cc_unit_state::__anonbf125d3a2908
1582 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anonbf125d3a7708
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c84 .stencil_write_mask = {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
1000 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1005 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
3206 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3207 bool back_same = state->dynamic.stencil_write_mask
[all...]
/xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
H A Dv3dv_cmd_buffer.c41 .stencil_write_mask =
1848 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1849 sizeof(src->stencil_write_mask))) {
1850 dest->stencil_write_mask = src->stencil_write_mask;
2842 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask & 0xff;
2844 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask & 0xff;
H A Dv3dvx_pipeline.c290 config.stencil_write_mask = write_mask;
H A Dv3dvx_cmd_buffer.c1067 config.stencil_write_mask =
1068 i == 0 ? dynamic_state->stencil_write_mask.front :
1069 dynamic_state->stencil_write_mask.back;
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Dbrw_structs.h587 unsigned int stencil_write_mask:8; member in struct:brw_cc_unit_state::__anonfa77c8dc2908
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.h1602 unsigned int stencil_write_mask:8; member in struct:gen4_cc_unit_state::__anon5ecad36c2908
2645 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon5ecad36c7708
H A Dgen5_render.h1690 unsigned int stencil_write_mask:8; member in struct:gen5_cc_unit_state::__anon62d5648d2908
2725 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon62d5648d7708
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.h1602 unsigned int stencil_write_mask:8; member in struct:gen4_cc_unit_state::__anon763174a02908
2645 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon763174a07708
H A Dgen5_render.h1690 unsigned int stencil_write_mask:8; member in struct:gen5_cc_unit_state::__anon7a3c05c12908
2725 unsigned int stencil_write_mask:8; member in struct:gen6_depth_stencil_state::__anon7a3c05c17708
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
H A Dv3dx_state.c223 config.stencil_write_mask = front->writemask;
242 config.stencil_write_mask = back->writemask;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/v3d/
H A Dv3dx_state.c223 config.stencil_write_mask = front->writemask;
242 config.stencil_write_mask = back->writemask;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c95 .stencil_write_mask =
200 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
201 sizeof(src->stencil_write_mask))) {
202 dest->stencil_write_mask = src->stencil_write_mask;
1490 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1494 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
5087 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
5088 bool back_same = state->dynamic.stencil_write_mask
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/asahi/
H A Dagx_state.c195 cfg.stencil_write_mask = st.writemask;
204 cfg.stencil_write_mask = 0xFF;

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