| H A D | ac_nir_lower_tess_io_to_mem.c | 300 nir_ssa_def *tcs_num_patches = nir_build_load_tcs_num_patches_amd(b); local in function:hs_output_lds_offset 302 nir_ssa_def *output_patch0_offset = nir_imul(b, input_patch_size, tcs_num_patches); 333 nir_ssa_def *tcs_num_patches = nir_build_load_tcs_num_patches_amd(b); local in function:hs_per_vertex_output_vmem_offset 334 nir_ssa_def *attr_stride = nir_imul(b, tcs_num_patches, nir_imul_imm(b, out_vertices_per_patch, 16u)); 356 nir_ssa_def *tcs_num_patches = nir_build_load_tcs_num_patches_amd(b); local in function:hs_per_patch_output_vmem_offset 358 nir_ssa_def *per_patch_data_offset = nir_imul(b, tcs_num_patches, per_vertex_output_patch_size); 361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) 365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); 711 unsigned tcs_num_patches; member in struct:__anon9214dccf0208 740 return nir_imm_int(b, st->tcs_num_patches); 747 ac_nir_lower_tess_to_const(nir_shader * shader,unsigned patch_vtx_in,unsigned tcs_num_patches,unsigned options) argument [all...] |