Searched refs:thrsw (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dqpu_schedule.c351 if (inst->sig.thrsw) {
662 merge.sig.thrsw |= b->sig.thrsw;
705 if (prev_inst->inst->qpu.sig.thrsw)
763 if (inst->sig.thrsw)
1084 /* No emitting our thrsw while the previous thrsw hasn't happened yet. */
1132 /* There should be nothing in a thrsw inst being scheduled other than
1144 sig.thrsw = true;
1163 merge_inst->qpu.sig.thrsw
1483 struct qinst *thrsw = vir_nop(); local in function:v3d_qpu_schedule_instructions
[all...]
H A Dvir_opt_redundant_flags.c110 /* Flags aren't preserved across a thrsw. */
111 if (inst->qpu.sig.thrsw)
H A Dqpu_validate.c224 if (inst->sig.thrsw) {
233 * last-thrsw signal.
H A Dvir_dump.c213 if (sig->thrsw)
214 fprintf(stderr, "; thrsw");
H A Dvir_register_allocate.c121 * thrsw.
276 /* If we didn't have a last-thrsw inserted by nir_to_vir and
292 /* Make sure c->last_thrsw is the actual last thrsw, not just one we
591 if (inst->qpu.sig.thrsw) {
H A Dvir.c79 inst->qpu.sig.thrsw) {
H A Dnir_to_vir.c123 c->last_thrsw->qpu.sig.thrsw = true;
2396 if (inst->qpu.sig.thrsw)
2420 * thrsw.
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dqpu_schedule.c391 if (inst->sig.thrsw) {
976 merge.sig.thrsw |= b->sig.thrsw;
1030 if (prev_inst->inst->qpu.sig.thrsw)
1091 /* If we are in a thrsw delay slot check that this instruction
1128 if (inst->sig.thrsw)
1161 * it in the delay slots of a thrsw, which is not
1538 * This is called when trying to merge a thrsw back into the instruction stream
1539 * of instructions that were scheduled *before* the thrsw signal to fill its
1540 * delay slots. Because the actual execution of the thrsw happen
2416 struct qinst *thrsw = vir_nop(); local in function:v3d_qpu_schedule_instructions
[all...]
H A Dvir_opt_redundant_flags.c110 /* Flags aren't preserved across a thrsw.
115 if (inst->qpu.sig.thrsw)
H A Dqpu_validate.c236 if (inst->sig.thrsw) {
245 * last-thrsw signal.
H A Dvir_dump.c220 if (sig->thrsw)
221 fprintf(stderr, "; thrsw");
H A Dvir_register_allocate.c140 * thrsw.
353 /* Make sure c->last_thrsw is the actual last thrsw, not just one we
389 * invalidated through thrsw), so running out of physical registers
751 if (inst->qpu.sig.thrsw) {
816 /* TMU spills inject thrsw signals that invalidate
H A Dnir_to_vir.c164 c->last_thrsw->qpu.sig.thrsw = true;
3908 if (inst->qpu.sig.thrsw)
3918 * start of the last thread section, which may include adding a new thrsw
3948 * thrsw.
3985 struct qinst *thrsw,
3990 c->last_thrsw = thrsw;
3984 vir_restore_last_thrsw(struct v3d_compile * c,struct qinst * thrsw,bool scoreboard_lock) argument
H A Dvir.c84 inst->qpu.sig.thrsw) {
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_disasm.c206 if (!sig->thrsw &&
222 if (sig->thrsw)
223 append(disasm, "; thrsw");
H A Dqpu_instr.h43 bool thrsw:1; member in struct:v3d_qpu_sig
H A Dqpu_pack.c107 #define THRSW .thrsw = true
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_disasm.c204 if (!sig->thrsw &&
218 if (sig->thrsw)
219 append(disasm, "; thrsw");
H A Dqpu_instr.h43 bool thrsw:1; member in struct:v3d_qpu_sig
H A Dqpu_pack.c106 #define THRSW .thrsw = true
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.2.8.rst80 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
H A D18.3.2.rst137 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
H A D21.2.2.rst190 - broadcom/compiler: force a last thrsw for spilling
H A D19.0.0.rst755 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
869 - v3d: Fix the check for "is the last thrsw inside control flow"
H A D19.1.0.rst1391 - v3d: Fix the check for "is the last thrsw inside control flow"
1470 - v3d: Fix an invalid reuse of flags generation from before a thrsw.

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