Searched refs:tile_split (Results 1 - 25 of 44) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h108 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
136 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h108 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
139 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_bo_helper.c95 static unsigned eg_tile_split_opp(unsigned tile_split) argument
97 switch (tile_split) {
98 case 0: tile_split = 64; break;
99 case 1: tile_split = 128; break;
100 case 2: tile_split = 256; break;
101 case 3: tile_split = 512; break;
103 case 4: tile_split = 1024; break;
104 case 5: tile_split = 2048; break;
105 case 6: tile_split = 4096; break;
107 return tile_split;
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H A Devergreen_accel.c75 unsigned eg_tile_split(unsigned tile_split) argument
77 switch (tile_split) {
78 case 64: tile_split = 0; break;
79 case 128: tile_split = 1; break;
80 case 256: tile_split = 2; break;
81 case 512: tile_split = 3; break;
83 case 1024: tile_split = 4; break;
84 case 2048: tile_split = 5; break;
85 case 4096: tile_split = 6; break;
87 return tile_split;
206 uint32_t tile_split, macro_aspect, bankw, bankh; local in function:evergreen_set_render_target
691 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local in function:evergreen_set_tex_resource
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/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_surface.c655 unsigned bpe, unsigned tile_split,
669 if (tileb > tile_split && tile_split) {
670 slice_pt = tileb / tile_split;
734 switch (surf->tile_split) {
779 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
821 surf->tile_split, 0, 0);
905 /* compute best tile_split, bankw, bankh, mtilea
918 surf->tile_split = 1024;
922 tileb = MIN2(surf->tile_split, 6
652 eg_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1072 si_gb_tile_mode(uint32_t gb_tile_mode,unsigned * num_pipes,unsigned * num_banks,uint32_t * macro_tile_aspect,uint32_t * bank_w,uint32_t * bank_h,uint32_t * tile_split) argument
1617 si_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned num_pipes,unsigned num_banks,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1871 unsigned tile_split, sample_split; local in function:cik_get_2d_params
2215 cik_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned tile_split,unsigned num_pipes,unsigned num_banks,uint64_t offset,unsigned start_level) argument
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H A Dradeon_surface.h133 uint32_t tile_split; member in struct:radeon_surface
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Devergreen_accel.c78 unsigned eg_tile_split(unsigned tile_split) argument
80 switch (tile_split) {
81 case 64: tile_split = 0; break;
82 case 128: tile_split = 1; break;
83 case 256: tile_split = 2; break;
84 case 512: tile_split = 3; break;
85 case 1024: tile_split = 4; break;
86 case 2048: tile_split = 5; break;
88 case 4096: tile_split = 6; break;
90 return tile_split;
209 uint32_t tile_split, macro_aspect, bankw, bankh; local in function:evergreen_set_render_target
699 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local in function:evergreen_set_tex_resource
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c624 static unsigned eg_tile_split(unsigned tile_split) argument
626 switch (tile_split) {
627 case 0: tile_split = 64; break;
628 case 1: tile_split = 128; break;
629 case 2: tile_split = 256; break;
630 case 3: tile_split = 512; break;
632 case 4: tile_split = 1024; break;
633 case 5: tile_split = 2048; break;
634 case 6: tile_split = 4096; break;
636 return tile_split;
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c36 tileb = MIN2(surf->u.legacy.tile_split, tileb);
154 surf_drm->tile_split = surf_ws->u.legacy.tile_split;
196 surf_ws->u.legacy.tile_split = surf_drm->tile_split;
H A Dradeon_drm_bo.c846 static unsigned eg_tile_split(unsigned tile_split) argument
848 switch (tile_split) {
849 case 0: tile_split = 64; break;
850 case 1: tile_split = 128; break;
851 case 2: tile_split = 256; break;
852 case 3: tile_split = 512; break;
854 case 4: tile_split = 1024; break;
855 case 5: tile_split = 2048; break;
856 case 6: tile_split = 4096; break;
858 return tile_split;
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/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_bo.c848 static unsigned eg_tile_split(unsigned tile_split) argument
850 switch (tile_split) {
851 case 0: tile_split = 64; break;
852 case 1: tile_split = 128; break;
853 case 2: tile_split = 256; break;
854 case 3: tile_split = 512; break;
856 case 4: tile_split = 1024; break;
857 case 5: tile_split = 2048; break;
858 case 6: tile_split = 4096; break;
860 return tile_split;
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H A Dradeon_drm_surface.c36 tileb = MIN2(surf->u.legacy.tile_split, tileb);
154 surf_drm->tile_split = surf_ws->u.legacy.tile_split;
196 surf_ws->u.legacy.tile_split = surf_drm->tile_split;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c852 eg_tile_split(unsigned tile_split) argument
854 switch (tile_split) {
856 tile_split = 64;
859 tile_split = 128;
862 tile_split = 256;
865 tile_split = 512;
869 tile_split = 1024;
872 tile_split = 2048;
875 tile_split = 4096;
878 return tile_split;
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_dma.c110 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt; local in function:si_dma_copy_tile
146 tile_split = util_logbase2(tiled->surface.u.legacy.tile_split >> 6);
171 radeon_emit(cs, (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27));
H A Dcik_sdma.c90 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
347 tiled->surface.u.legacy.tile_split <= 4096 &&
391 ssrc->surface.u.legacy.tile_split <= 4096 &&
392 sdst->surface.u.legacy.tile_split <= 4096 &&
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dradeon_video.c180 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
H A Devergreen_state.c64 static unsigned eg_tile_split(unsigned tile_split) argument
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
76 return tile_split;
730 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local in function:evergreen_fill_tex_resource_words
1120 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local in function:evergreen_set_color_surface_common
1356 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local in function:evergreen_init_depth_surface
3776 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0; local in function:evergreen_dma_copy_tile
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_video.c171 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dradeon_video.c180 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
H A Devergreen_state.c64 static unsigned eg_tile_split(unsigned tile_split) argument
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
76 return tile_split;
736 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local in function:evergreen_fill_tex_resource_words
1126 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local in function:evergreen_set_color_surface_common
1362 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local in function:evergreen_init_depth_surface
3789 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0; local in function:evergreen_dma_copy_tile
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_bo.c1184 static unsigned eg_tile_split(unsigned tile_split) argument
1186 switch (tile_split) {
1187 case 0: tile_split = 64; break;
1188 case 1: tile_split = 128; break;
1189 case 2: tile_split = 256; break;
1190 case 3: tile_split = 512; break;
1192 case 4: tile_split = 1024; break;
1193 case 5: tile_split = 2048; break;
1194 case 6: tile_split = 4096; break;
1196 return tile_split;
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/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h98 unsigned tile_split:13; /* max 4K */ member in struct:legacy_surf_layout
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c797 tileb = MIN2(surf->u.legacy.tile_split, tileb);
855 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
1110 surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
1117 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
2458 static unsigned eg_tile_split(unsigned tile_split) argument
2460 switch (tile_split) {
2462 tile_split = 64;
2465 tile_split = 128;
2468 tile_split = 256;
2471 tile_split
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h144 unsigned tile_split; member in struct:radeon_bo_metadata::__anon996f74f1010a::__anon996f74f10208
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c65 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
383 tiled->surface.u.legacy.tile_split <= 4096 && pitch_tile_max < (1 << 11) &&

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