| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/ |
| H A D | vc4_validate_shaders.c | 153 int tmu) 166 &validation_state->tmu_setup[tmu], 173 validation_state->tmu_setup[tmu].p_offset[i] = ~0; 189 int tmu = waddr > QPU_W_TMU0_B; local in function:check_tmu_write 191 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; 232 validation_state->tmu_setup[tmu].p_offset[1] = 241 validation_state->tmu_setup[tmu].is_direct = true; 251 if (validation_state->tmu_write_count[tmu] >= 4) { 253 tmu); 256 validation_state->tmu_setup[tmu] 151 record_texture_sample(struct vc4_validated_shader_info * validated_shader,struct vc4_shader_validation_state * validation_state,int tmu) argument [all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/ |
| H A D | vc4_validate_shaders.c | 153 int tmu) 166 &validation_state->tmu_setup[tmu], 173 validation_state->tmu_setup[tmu].p_offset[i] = ~0; 189 int tmu = waddr > QPU_W_TMU0_B; local in function:check_tmu_write 191 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; 232 validation_state->tmu_setup[tmu].p_offset[1] = 241 validation_state->tmu_setup[tmu].is_direct = true; 251 if (validation_state->tmu_write_count[tmu] >= 4) { 253 tmu); 256 validation_state->tmu_setup[tmu] 151 record_texture_sample(struct vc4_validated_shader_info * validated_shader,struct vc4_shader_validation_state * validation_state,int tmu) argument [all...] |
| /xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/ |
| H A D | v3d33_tex.c | 183 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]); local in function:v3d33_vir_emit_tex 186 tmu->uniform = texture_u[i];
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| H A D | nir_to_vir.c | 251 if (c->tmu.flush_count >= MAX_TMU_QUEUE_SIZE) 255 c->tmu.output_fifo_size + components > 16 / c->threads; 265 if (c->tmu.flush_count == 0) 271 for (int i = 0; i < c->tmu.flush_count; i++) { 272 if (c->tmu.flush[i].component_mask > 0) { 273 nir_dest *dest = c->tmu.flush[i].dest; 277 if (c->tmu.flush[i].component_mask & (1 << j)) { 288 c->tmu.output_fifo_size = 0; 289 c->tmu.flush_count = 0; 290 _mesa_set_clear(c->tmu 456 struct qinst *tmu; local in function:emit_tmu_general_address_write [all...] |
| H A D | v3d_compiler.h | 623 } tmu; member in struct:v3d_compile
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| H A D | vir.c | 581 c->tmu.outstanding_regs = _mesa_pointer_set_create(c);
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| /xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/ |
| H A D | v3d33_tex.c | 175 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]); local in function:v3d33_vir_emit_tex 178 tmu->uniform = texture_u[i];
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| H A D | nir_to_vir.c | 300 struct qinst *tmu; local in function:ntq_emit_tmu_general 306 tmu = vir_ADD_dest(c, tmua, offset, 310 tmu = vir_ADD_dest(c, tmua, offset, 313 tmu = vir_MOV_dest(c, tmua, offset); 318 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, 323 vir_set_cond(tmu, V3D_QPU_COND_IFA);
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| /xsrc/external/mit/xf86-video-mga/dist/src/ |
| H A D | mga_exa.c | 319 mgaCheckSourceTexture(int tmu, PicturePtr pPict) argument 397 PrepareSourceTexture(int tmu, PicturePtr pSrcPicture, PixmapPtr pSrc) argument 421 if (tmu == 1) 436 if (tmu == 1) {
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_program.c | 491 struct qinst *tmu; local in function:ntq_emit_tex 493 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r); 494 tmu->src[qir_get_tex_uniform_src(tmu)] = 500 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), 503 tmu->src[qir_get_tex_uniform_src(tmu)] = 515 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t); 516 tmu->src[qir_get_tex_uniform_src(tmu)] [all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 36 int tmu) 42 compiler->state.unit[tmu].texture_swizzle); 47 int tmu) 53 compiler->state.unit[tmu].texture_swizzle); 35 shadow_fail_value(struct r300_fragment_program_compiler * compiler,int tmu) argument 46 shadow_pass_value(struct r300_fragment_program_compiler * compiler,int tmu) argument
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_program.c | 481 struct qinst *tmu; local in function:ntq_emit_tex 483 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r); 484 tmu->src[qir_get_tex_uniform_src(tmu)] = 490 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), 493 tmu->src[qir_get_tex_uniform_src(tmu)] = 505 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t); 506 tmu->src[qir_get_tex_uniform_src(tmu)] [all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 36 int tmu) 42 compiler->state.unit[tmu].texture_swizzle); 47 int tmu) 53 compiler->state.unit[tmu].texture_swizzle); 35 shadow_fail_value(struct r300_fragment_program_compiler * compiler,int tmu) argument 46 shadow_pass_value(struct r300_fragment_program_compiler * compiler,int tmu) argument
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 273 - v3d/tex: don't configure tmu config 1 if not needed
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| H A D | 21.1.0.rst | 2345 - broadcom/compiler: fix end of tmu sequence detection
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| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | 1822 "description": "broadcom/compiler: define max number of tmu spills for compile strategies", [all...] |