| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_eu_util.c | 77 dst = vec8(dst);
78 src = vec8(src);
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| H A D | brw_reg.h | 1025 vec8(struct brw_reg reg) function in typeref:struct:brw_reg
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| H A D | brw_fs_generator.cpp | 441 struct brw_reg addr = vec8(brw_address_reg(0));
559 struct brw_reg addr = vec8(brw_address_reg(0));
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| H A D | brw_vec4_generator.cpp | 1418 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1455 struct brw_reg addr = vec8(brw_address_reg(0));
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| H A D | brw_eu_emit.c | 2247 dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
2290 dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
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| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_eu_util.c | 77 dst = vec8(dst);
78 src = vec8(src);
|
| H A D | brw_compile_ff_gs.c | 379 vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
425 brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
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| H A D | brw_reg.h | 1039 vec8(struct brw_reg reg) function in typeref:struct:brw_reg
|
| H A D | brw_fs_generator.cpp | 486 struct brw_reg addr = vec8(brw_address_reg(0));
646 struct brw_reg addr = vec8(brw_address_reg(0));
|
| H A D | brw_vec4_generator.cpp | 1432 struct brw_reg addr = vec8(brw_address_reg(0));
1484 scratch = vec8(scratch);
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| H A D | brw_eu_emit.c | 2427 dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
2469 dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| H A D | brw_ff_gs_emit.c | 350 vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
396 brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| H A D | brw_wm.c | 33 brw_ADD(p, brw_vec8_grf(X16, 0), vec8(x_uw), brw_negate(r1));
34 brw_ADD(p, brw_vec8_grf(Y16, 0), vec8(y_uw), brw_negate(__suboffset(r1, 1)));
|
| H A D | brw_eu_emit.c | 1569 dest = __retype_uw(vec8(dest));
1616 dest = __retype_uw(vec8(dest));
1755 dest = __retype_uw(vec8(brw_null_reg()));
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| H A D | brw_eu.h | 1671 static inline struct brw_reg vec8(struct brw_reg reg) function in typeref:struct:brw_reg
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| H A D | brw_wm.c | 33 brw_ADD(p, brw_vec8_grf(X16, 0), vec8(x_uw), brw_negate(r1));
34 brw_ADD(p, brw_vec8_grf(Y16, 0), vec8(y_uw), brw_negate(__suboffset(r1, 1)));
|
| H A D | brw_eu_emit.c | 1569 dest = __retype_uw(vec8(dest));
1616 dest = __retype_uw(vec8(dest));
1755 dest = __retype_uw(vec8(brw_null_reg()));
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| H A D | brw_eu.h | 1671 static inline struct brw_reg vec8(struct brw_reg reg) function in typeref:struct:brw_reg
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.0.0.rst | 862 - gallivm/nir: add vec8/16 support
1911 - nir/serialize: fix vec8 and vec16
1923 - nv50ir/nir: support vec8 and vec16
2255 - nir/serialize: serialize swizzles for vec8 and vec16
2256 - nir/serialize: serialize writemask for vec8 and vec16
2968 - nir+vtn: vec8+vec16 support
|
| H A D | 20.1.0.rst | 2418 - nir: Handle vec8/16 in bool_to_bitsize
2419 - nir: Handle vec8/16 in gather_ssa_types
2420 - nir: Handle vec8/16 in lower_phis_to_scalar
2421 - nir: Handle vec8/16 in lower_regs_to_ssa
2422 - nir: Handle vec8/16 in opt_split_alu_of_phi
2423 - nir: Treat vec8/16 as select in opt_peephole_select
2424 - nir: Handle vec8/16 in opt_undef_vecN
2425 - nir: Handle vec8/16 in nir_shrink_array_vars
|
| H A D | 20.2.0.rst | 2677 - nir: Support vec8/vec16 in nir_lower_bit_size
|
| H A D | 20.3.0.rst | 2646 - intel/fs: Add support for vec8 and vec16 ops
|
| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | [all...] |