Searched refs:vectors (Results 1 - 25 of 48) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/main/
H A Duniform_query.cpp769 const unsigned vectors = uni->type->matrix_columns; local in function:_mesa_propagate_uniforms_to_driver_storage
781 store->element_stride - (vectors * store->vector_stride);
783 (uint8_t *) (&uni->storage[array_index * (dmul * components * vectors)].i);
786 printf("%s: %p[%d] components=%u vectors=%u count=%u vector_stride=%u "
789 vectors, count, store->vector_stride, extra_stride);
802 memcpy(dst, src, src_vector_byte_stride * vectors);
803 src += src_vector_byte_stride * vectors;
804 dst += store->vector_stride * vectors;
810 memcpy(dst, src, src_vector_byte_stride * vectors * count);
811 src += src_vector_byte_stride * vectors * coun
1245 copy_uniform_matrix_to_storage(gl_constant_value * storage,GLsizei count,const void * values,const unsigned size_mul,const unsigned offset,const unsigned components,const unsigned vectors,bool transpose,unsigned cols,unsigned rows,enum glsl_base_type basicType) argument
1320 const unsigned vectors = uni->type->matrix_columns; local in function:_mesa_uniform_matrix
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/xsrc/external/mit/mesa-demos/dist/src/egl/openvg/
H A Dtext.c127 path_append(VGPath path, VGubyte segment, const FT_Vector **vectors) argument
149 coords[2 * i + 0] = (float) vectors[i]->x / 64.0f;
150 coords[2 * i + 1] = (float) vectors[i]->y / 64.0f;
178 const FT_Vector *vectors[2] = { control, to }; local in function:decompose_conic_to
180 return path_append(path, VG_QUAD_TO, vectors);
188 const FT_Vector *vectors[3] = { control1, control2, to }; local in function:decompose_cubic_to
190 return path_append(path, VG_CUBIC_TO, vectors);
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Duniform_query.cpp837 const unsigned vectors = uni->type->matrix_columns; local in function:_mesa_propagate_uniforms_to_driver_storage
849 store->element_stride - (vectors * store->vector_stride);
851 (uint8_t *) (&uni->storage[array_index * (dmul * components * vectors)].i);
854 printf("%s: %p[%d] components=%u vectors=%u count=%u vector_stride=%u "
857 vectors, count, store->vector_stride, extra_stride);
870 memcpy(dst, src, src_vector_byte_stride * vectors);
871 src += src_vector_byte_stride * vectors;
872 dst += store->vector_stride * vectors;
878 memcpy(dst, src, src_vector_byte_stride * vectors * count);
879 src += src_vector_byte_stride * vectors * coun
1450 copy_uniform_matrix_to_storage(struct gl_context * ctx,gl_constant_value * storage,struct gl_uniform_storage * const uni,unsigned count,const void * values,const unsigned size_mul,const unsigned offset,const unsigned components,const unsigned vectors,bool transpose,unsigned cols,unsigned rows,enum glsl_base_type basicType,bool flush) argument
1701 const unsigned vectors = uni->type->matrix_columns; local in function:_mesa_uniform_matrix
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c614 static struct reg vectors[512*4+1]; variable in typeref:struct:reg[]
636 for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) {
638 vectors[i].idx = i;
639 vectors[i].closest = tmp;
640 vectors[i].flags = ISFLOAT|ISVEC;
645 vectors[ARRAY_SIZE(vectors)-1].idx = -1;
795 for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++)
796 print_reg( &vectors[i] );
903 int sz = header.vectors
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H A Dr200_state_init.c176 h.vectors.cmd_type = RADEON_CMD_VECTORS;
177 h.vectors.offset = offset;
178 h.vectors.stride = stride;
179 h.vectors.count = count;
285 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
286 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
287 OUT_BATCH_TABLE((data), h.vectors.count); \
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_sanity.c336 static struct reg vectors[512*4+1]; variable in typeref:struct:reg[]
358 for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) {
360 vectors[i].idx = i;
361 vectors[i].closest = tmp;
362 vectors[i].flags = ISFLOAT|ISVEC;
367 vectors[ARRAY_SIZE(vectors)-1].idx = -1;
517 for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++)
518 print_reg( &vectors[i] );
625 int sz = header.vectors
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H A Dradeon_state_init.c171 h.vectors.cmd_type = RADEON_CMD_VECTORS;
172 h.vectors.offset = offset;
173 h.vectors.stride = stride;
174 h.vectors.count = count;
247 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
248 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
249 OUT_BATCH_TABLE((data), h.vectors.count); \
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c614 static struct reg vectors[512*4+1]; variable in typeref:struct:reg[]
636 for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) {
638 vectors[i].idx = i;
639 vectors[i].closest = tmp;
640 vectors[i].flags = ISFLOAT|ISVEC;
645 vectors[ARRAY_SIZE(vectors)-1].idx = -1;
795 for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++)
796 print_reg( &vectors[i] );
903 int sz = header.vectors
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H A Dr200_state_init.c176 h.vectors.cmd_type = RADEON_CMD_VECTORS;
177 h.vectors.offset = offset;
178 h.vectors.stride = stride;
179 h.vectors.count = count;
285 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
286 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
287 OUT_BATCH_TABLE((data), h.vectors.count); \
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_sanity.c336 static struct reg vectors[512*4+1]; variable in typeref:struct:reg[]
358 for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) {
360 vectors[i].idx = i;
361 vectors[i].closest = tmp;
362 vectors[i].flags = ISFLOAT|ISVEC;
367 vectors[ARRAY_SIZE(vectors)-1].idx = -1;
517 for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++)
518 print_reg( &vectors[i] );
625 int sz = header.vectors
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H A Dradeon_state_init.c170 h.vectors.cmd_type = RADEON_CMD_VECTORS;
171 h.vectors.offset = offset;
172 h.vectors.stride = stride;
173 h.vectors.count = count;
246 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
247 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
248 OUT_BATCH_TABLE((data), h.vectors.count); \
/xsrc/external/mit/mesa-demos/dist/src/objviewer/
H A Dglm.c83 /* _glmDot: compute the dot product of two vectors
98 /* _glmCross: compute the cross product of two vectors
135 /* _glmEqual: compares two vectors and returns TRUE if they are
154 /* _glmWeldVectors: eliminate (weld) vectors that are within an
157 * vectors - array of float[3]'s to be welded
158 * numvectors - number of float[3]'s in vectors
159 * epsilon - maximum difference between vectors
163 _glmWeldVectors(float* vectors, uint* numvectors, float epsilon) argument
170 memcpy(copies, vectors, (sizeof(float) * 3 * (*numvectors + 1)));
175 if (_glmEqual(&vectors[
1664 float* vectors; local in function:glmWeld
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/xsrc/external/mit/MesaLib/dist/docs/nir/
H A Dalu.rst41 performed on vectors, it performs the same operation on each component. Things
51 :cpp:member:`nir_alu_src::swizzle` field which allows them to act on vectors
54 instructions are often used (and required) for packing/unpacking vectors for
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/cso/
H A Dvelems.rst14 guaranteed to support 32-bit floating-point vectors of one to four components.
/xsrc/external/mit/MesaLib/dist/docs/gallium/cso/
H A Dvelems.rst14 guaranteed to support 32-bit floating-point vectors of one to four components.
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/sb/
H A Dnotes.markdown260 using the vectors of pointers to **value** class (node::src, node::dst)
280 register, etc), also it contains the maydef and mayuse vectors of
281 pointers to **value**s (similar to dst/src vectors in the **node**) to
306 we'll have both maydef and mayuse vectors for dst operand filled with
317 initializes src and dst value vectors for instruction nodes. Most
386 in node::src and node::dst vectors to the bytecode fields, converts
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sb/
H A Dnotes.markdown260 using the vectors of pointers to **value** class (node::src, node::dst)
280 register, etc), also it contains the maydef and mayuse vectors of
281 pointers to **value**s (similar to dst/src vectors in the **node**) to
306 we'll have both maydef and mayuse vectors for dst operand filled with
317 initializes src and dst value vectors for instruction nodes. Most
386 in node::src and node::dst vectors to the bytecode fields, converts
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D11.0.6.rst109 - llvmpipe: use simple coeffs calc for 128bit vectors
H A D20.1.8.rst115 - aco: fix byte_align_scalar for 3 dword vectors
H A D19.0.1.rst92 - nir: Add a new pass to lower array dereferences on vectors
H A D20.0.5.rst180 - nir: fix definition of imadsh_mix16 for vectors
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_arit.h66 LLVMValueRef vectors[],
H A Dlp_bld_arit.c672 * for byte vectors can do much better with psadbw.
673 * Using repeated shuffle/adds here. Note with multiple vectors
718 * Return the horizontal sums of 4 float vectors as a float4 vector.
773 * partially horizontally add 2-4 float vectors with length nx4,
778 * Return a vector of the same length as the initial vectors,
780 * The element order is independent of number of input vectors.
781 * For 3 vectors x0x1x2x3x4x5x6x7, y0y1y2y3y4y5y6y7, z0z1z2z3z4z5z6z7
787 LLVMValueRef vectors[],
799 /* only use this with at least 2 vectors, as it is sort of expensive
804 tmp[0] = vectors[
786 lp_build_hadd_partial4(struct lp_build_context * bld,LLVMValueRef vectors[],unsigned num_vecs) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_arit.h67 LLVMValueRef vectors[],
H A Dlp_bld_arit.c546 * for byte vectors can do much better with psadbw.
547 * Using repeated shuffle/adds here. Note with multiple vectors
592 * Return the horizontal sums of 4 float vectors as a float4 vector.
647 * partially horizontally add 2-4 float vectors with length nx4,
652 * Return a vector of the same length as the initial vectors,
654 * The element order is independent of number of input vectors.
655 * For 3 vectors x0x1x2x3x4x5x6x7, y0y1y2y3y4y5y6y7, z0z1z2z3z4z5z6z7
661 LLVMValueRef vectors[],
673 /* only use this with at least 2 vectors, as it is sort of expensive
678 tmp[0] = vectors[
660 lp_build_hadd_partial4(struct lp_build_context * bld,LLVMValueRef vectors[],unsigned num_vecs) argument
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