Searched refs:vpt (Results 1 - 25 of 26) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state_validate.c255 struct pipe_viewport_state *vpt = &nv50->viewports[i]; local in function:nv50_validate_viewport
261 PUSH_DATAf(push, vpt->translate[0]);
262 PUSH_DATAf(push, vpt->translate[1]);
263 PUSH_DATAf(push, vpt->translate[2]);
265 PUSH_DATAf(push, vpt->scale[0]);
266 PUSH_DATAf(push, vpt->scale[1]);
267 PUSH_DATAf(push, vpt->scale[2]);
274 util_viewport_zmin_zmax(vpt, nv50->rast->pipe.clip_halfz, &zmin, &zmax);
H A Dnv50_state.c1037 const struct pipe_viewport_state *vpt)
1044 if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1046 nv50->viewports[start_slot + i] = vpt[i];
1034 nv50_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state_validate.c255 struct pipe_viewport_state *vpt = &nv50->viewports[i]; local in function:nv50_validate_viewport
261 PUSH_DATAf(push, vpt->translate[0]);
262 PUSH_DATAf(push, vpt->translate[1]);
263 PUSH_DATAf(push, vpt->translate[2]);
265 PUSH_DATAf(push, vpt->scale[0]);
266 PUSH_DATAf(push, vpt->scale[1]);
267 PUSH_DATAf(push, vpt->scale[2]);
274 util_viewport_zmin_zmax(vpt, nv50->rast->pipe.clip_halfz, &zmin, &zmax);
H A Dnv50_state.c1039 const struct pipe_viewport_state *vpt)
1046 if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1048 nv50->viewports[start_slot + i] = vpt[i];
1036 nv50_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c543 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
601 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
782 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
783 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
784 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
785 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
786 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
787 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
H A Dradeon_context.h312 struct radeon_state_atom vpt; member in struct:r100_hw_state
H A Dradeon_state.c1373 RADEON_STATECHANGE( rmesa, vpt );
1375 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1376 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1377 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1378 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1379 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1380 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
H A Dradeon_ioctl.c74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c543 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
601 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
782 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
783 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
784 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
785 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
786 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
787 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
H A Dradeon_context.h312 struct radeon_state_atom vpt; member in struct:r100_hw_state
H A Dradeon_state.c1374 RADEON_STATECHANGE( rmesa, vpt );
1376 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1377 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1378 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1379 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1380 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1381 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
H A Dradeon_ioctl.c73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_state_init.c657 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
763 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1060 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1061 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1062 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1063 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1064 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1065 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
H A Dr200_context.h483 struct radeon_state_atom vpt; member in struct:r200_hw_state
H A Dr200_state.c1567 R200_STATECHANGE( rmesa, vpt );
1569 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1570 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1571 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1572 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1573 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1574 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
H A Dr200_cmdbuf.c68 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_state_init.c657 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
763 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1060 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1061 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1062 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1063 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1064 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1065 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
H A Dr200_context.h483 struct radeon_state_atom vpt; member in struct:r200_hw_state
H A Dr200_state.c1568 R200_STATECHANGE( rmesa, vpt );
1570 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1571 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1572 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1573 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1574 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1575 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
H A Dr200_cmdbuf.c68 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_state.c418 const struct pipe_viewport_state *vpt)
422 nv30->viewport = *vpt;
415 nv30_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_state.c429 const struct pipe_viewport_state *vpt)
433 nv30->viewport = *vpt;
426 nv30_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_state.c936 const struct pipe_viewport_state *vpt)
943 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
945 nvc0->viewports[start_slot + i] = vpt[i];
933 nvc0_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_state.c962 const struct pipe_viewport_state *vpt)
969 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
971 nvc0->viewports[start_slot + i] = vpt[i];
959 nvc0_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_state.cpp635 const struct pipe_viewport_state *vpt)
639 ctx->viewport = *vpt;
632 swr_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt) argument

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