Searched refs:wm (Results 1 - 25 of 106) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dgen4_blorp_exec.h113 blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) {
116 wm.SamplerCount = (GEN_GEN != 5);
117 wm.BindingTableEntryCount = 2;
119 wm.SamplerStatePointer = dynamic_state_address(batch, sampler);
123 wm.DispatchGRFStartRegisterForConstantSetupData0 =
125 wm.SetupURBEntryReadLength = prog_data->num_varying_inputs * 2;
126 wm.SetupURBEntryReadOffset = 0;
128 wm.DepthCoefficientURBReadOffset = 1;
129 wm.PixelShaderKillsPixel = prog_data->uses_kill;
130 wm
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H A Dgen6_sampler_state.c44 OUT_BATCH(brw->wm.base.sampler_offset);
H A Dbrw_binding_tables.c133 const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
137 &brw->wm.base);
257 OUT_BATCH(brw->wm.base.bind_bo_offset);
292 OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
H A DgenX_state_upload.c1078 brw_wm_prog_data(brw->wm.base.prog_data);
1397 brw_wm_prog_data(brw->wm.base.prog_data);
1708 brw_wm_prog_data(brw->wm.base.prog_data);
1803 brw_wm_prog_data(brw->wm.base.prog_data);
1807 UNUSED struct brw_stage_state *stage_state = &brw->wm.base;
1830 brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
1833 brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
1837 wm._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1838 wm._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1839 wm
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H A Dbrw_curbe.c81 const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16;
131 fprintf(stderr, "curbe wm %d+%d clip %d+%d vs %d+%d\n",
231 brw_populate_constant_data(brw, fp, &brw->wm.base, &buf[offset],
232 brw->wm.base.prog_data->param,
233 brw->wm.base.prog_data->nr_params);
H A Dbrw_wm.c154 brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
166 &brw->wm.base.prog_offset, &brw->wm.base.prog_data);
511 &brw->wm.base.prog_offset, &brw->wm.base.prog_data,
580 uint32_t old_prog_offset = brw->wm.base.prog_offset;
581 struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data;
592 brw->wm.base.prog_offset = old_prog_offset;
593 brw->wm.base.prog_data = old_prog_data;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dgen4_blorp_exec.h108 blorp_emit_dynamic(blorp_batch, GENX(WM_STATE), wm, 64, &offset) {
111 wm.SamplerCount = (GFX_VER != 5);
112 wm.BindingTableEntryCount = 2;
114 wm.SamplerStatePointer = dynamic_state_address(blorp_batch, sampler);
118 wm.DispatchGRFStartRegisterForConstantSetupData0 =
120 wm.SetupURBEntryReadLength = prog_data->num_varying_inputs * 2;
121 wm.SetupURBEntryReadOffset = 0;
123 wm.DepthCoefficientURBReadOffset = 1;
124 wm.PixelShaderKillsPixel = prog_data->uses_kill;
125 wm
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dgfx4_blorp_exec.h113 blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) {
116 wm.SamplerCount = (GFX_VER != 5);
117 wm.BindingTableEntryCount = 2;
119 wm.SamplerStatePointer = dynamic_state_address(batch, sampler);
123 wm.DispatchGRFStartRegisterForConstantSetupData0 =
125 wm.SetupURBEntryReadLength = prog_data->num_varying_inputs * 2;
126 wm.SetupURBEntryReadOffset = 0;
128 wm.DepthCoefficientURBReadOffset = 1;
129 wm.PixelShaderKillsPixel = prog_data->uses_kill;
130 wm
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H A Dgfx6_sampler_state.c44 OUT_BATCH(brw->wm.base.sampler_offset);
H A Dbrw_binding_tables.c133 const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
137 &brw->wm.base);
257 OUT_BATCH(brw->wm.base.bind_bo_offset);
292 OUT_BATCH(brw->wm.base.bind_bo_offset); /* wm/ps */
H A DgenX_state_upload.c1068 brw_wm_prog_data(brw->wm.base.prog_data);
1387 brw_wm_prog_data(brw->wm.base.prog_data);
1698 brw_wm_prog_data(brw->wm.base.prog_data);
1793 brw_wm_prog_data(brw->wm.base.prog_data);
1797 UNUSED struct brw_stage_state *stage_state = &brw->wm.base;
1820 brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
1823 brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
1827 wm._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1828 wm._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1829 wm
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H A Dbrw_curbe.c81 const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16;
131 fprintf(stderr, "curbe wm %d+%d clip %d+%d vs %d+%d\n",
231 brw_populate_constant_data(brw, fp, &brw->wm.base, &buf[offset],
232 brw->wm.base.prog_data->param,
233 brw->wm.base.prog_data->nr_params);
H A Dbrw_wm.c165 brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
177 &brw->wm.base.prog_offset, &brw->wm.base.prog_data);
552 &brw->wm.base.prog_offset, &brw->wm.base.prog_data,
622 uint32_t old_prog_offset = brw->wm.base.prog_offset;
623 struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data;
634 brw->wm.base.prog_offset = old_prog_offset;
635 brw->wm.base.prog_data = old_prog_data;
/xsrc/external/mit/libXt/dist/include/X11/
H A DVendorP.h96 WMShellPart wm; member in struct:__anon61a27edb0308
H A DShellP.h214 WMShellPart wm; member in struct:__anon46fc50250b08
256 WMShellPart wm; member in struct:__anon46fc50250e08
296 WMShellPart wm; member in struct:__anon46fc50251108
342 WMShellPart wm; member in struct:__anon46fc50251408
425 WMShellPart wm; member in struct:__anon46fc50251708
/xsrc/external/mit/libXt/dist/src/
H A DShell.c323 Offset(wm.title), XtRString, NULL},
325 Offset(wm.title_encoding),
328 Offset(wm.wm_timeout), XtRImmediate,(XtPointer)DEFAULT_WM_TIMEOUT},
330 Offset(wm.wait_for_wm), XtRImmediate, (XtPointer)True},
332 Offset(wm.transient), XtRImmediate, (XtPointer)False},
335 Offset(wm.base_width),
338 Offset(wm.base_height),
341 Offset(wm.win_gravity),
344 Offset(wm.size_hints.min_width),
347 Offset(wm
1804 WMShellPart *wm = &((WMShellWidget) w)->wm; local in function:GetGeometry
2045 Boolean wm; local in function:RootGeometryManager
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/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_wmark.c43 unsigned int wm; member in struct:wm_info
298 tab[i].wm, tab[i].freq);
311 return (tab[i].wm & ~0xffffff) | ((tab[i].wm >> 12) & 0xfff);
313 return tab[i].wm;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_wmark.c43 unsigned int wm; member in struct:wm_info
298 tab[i].wm, tab[i].freq);
311 return (tab[i].wm & ~0xffffff) | ((tab[i].wm >> 12) & 0xfff);
313 return tab[i].wm;
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810_wmark.c42 unsigned int wm; member in struct:wm_info
297 tab[i].wm, tab[i].freq);
310 return (tab[i].wm & ~0xffffff) | ((tab[i].wm >> 12) & 0xfff);
312 return tab[i].wm;
/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740_driver.c1094 unsigned int wm = 0x18120000; local in function:I740CalcFIFO
1110 if (freq > 200) wm = 0x18120000;
1111 else if (freq > 175) wm = 0x16110000;
1112 else if (freq > 135) wm = 0x120E0000;
1113 else wm = 0x100D0000;
1115 if (freq > 200) wm = 0x18120000;
1116 else if (freq > 175) wm = 0x16110000;
1117 else if (freq > 135) wm = 0x120E0000;
1118 else wm = 0x100D0000;
1123 if (freq > 140) wm
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_asm.h119 unsigned wm = 0; local in function:inst_write_mask_compose
123 wm |= (1 << i);
127 return wm;
/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_genX_exec.h764 blorp_emit(batch, GENX(3DSTATE_WM), wm);
863 blorp_emit(batch, GENX(3DSTATE_WM), wm) {
866 wm.DepthBufferClear = true;
869 wm.DepthBufferResolveEnable = true;
872 wm.HierarchicalDepthBufferResolveEnable = true;
881 wm.ThreadDispatchEnable = true;
884 wm.PixelShaderKillsPixel = true;
887 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
888 wm.MultisampleDispatchMode =
892 wm
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/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h834 blorp_emit(batch, GENX(3DSTATE_WM), wm);
940 blorp_emit(batch, GENX(3DSTATE_WM), wm) {
943 wm.DepthBufferClear = true;
946 wm.DepthBufferResolveEnable = true;
949 wm.HierarchicalDepthBufferResolveEnable = true;
958 wm.ThreadDispatchEnable = true;
959 wm.PixelShaderComputedDepthMode = prog_data->computed_depth_mode;
963 wm.PixelShaderKillsPixel = true;
966 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
967 wm
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/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dr600_shader.h229 // wm
249 #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
250 cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
253 #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
254 cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
259 #define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
261 R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
262 R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dr600_shader.h229 // wm
249 #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
250 cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
253 #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
254 cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
259 #define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
261 R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
262 R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))

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