Searched refs:zb (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3270 struct si_surface *zb = (struct si_surface *)state->zsbuf; local in function:si_emit_framebuffer_state
3271 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3272 unsigned db_z_info = zb->db_z_info;
3273 unsigned db_stencil_info = zb->db_stencil_info;
3274 unsigned db_htile_surface = zb->db_htile_surface;
3277 zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3282 vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3299 unsigned level = zb->base.u.tex.level;
3302 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3303 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3208 struct si_surface *zb = (struct si_surface*)state->zsbuf; local in function:si_emit_framebuffer_state
3209 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3213 zb->base.texture->nr_samples > 1 ?
3219 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3220 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3221 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3224 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3226 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3227 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3228 radeon_emit(cs, S_028044_BASE_HI(zb
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_state.cpp976 struct pipe_surface *zb = ctx->framebuffer.zsbuf; local in function:swr_invalidate_buffers_after_ctx_change
977 if (zb) {
978 struct swr_resource *res = swr_resource(zb->texture);
983 swr_invalidate_render_target(pipe, SWR_ATTACHMENT_DEPTH, zb->width, zb->height);
984 swr_invalidate_render_target(pipe, SWR_ATTACHMENT_STENCIL, zb->width, zb->height);
1192 struct pipe_surface *zb = fb->zsbuf; local in function:swr_update_derived
1193 if (zb && swr_resource(zb
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/
H A Dswr_state.cpp1100 struct pipe_surface *zb = ctx->framebuffer.zsbuf; local in function:swr_invalidate_buffers_after_ctx_change
1101 if (zb) {
1102 struct swr_resource *res = swr_resource(zb->texture);
1107 swr_invalidate_render_target(pipe, SWR_ATTACHMENT_DEPTH, zb->width, zb->height);
1108 swr_invalidate_render_target(pipe, SWR_ATTACHMENT_STENCIL, zb->width, zb->height);
1340 struct pipe_surface *zb = fb->zsbuf; local in function:swr_update_derived
1341 if (zb && swr_resource(zb
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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.cpp799 UINT_32 zb = pIn->slice; local in function:Addr::V2::Gfx9Lib::HwlComputeCmaskAddrFromCoord
803 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
874 UINT_32 zb = pIn->slice; local in function:Addr::V2::Gfx9Lib::HwlComputeHtileAddrFromCoord
878 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
1029 UINT_32 zb = pIn->slice / output.metaBlkDepth; local in function:Addr::V2::Gfx9Lib::HwlComputeDccAddrFromCoord
1033 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
4786 UINT_32 zb = pIn->slice / localOut.blockSlices + + mipStartPos.d; local in function:Addr::V2::Gfx9Lib::HwlComputeSurfaceAddrFromCoordTiled
4791 UINT_64 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.cpp887 UINT_32 zb = pIn->slice; local in function:Addr::V2::Gfx9Lib::HwlComputeCmaskAddrFromCoord
891 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
964 UINT_32 zb = pIn->slice; local in function:Addr::V2::Gfx9Lib::HwlComputeHtileAddrFromCoord
968 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
1128 UINT_32 zb = pIn->slice / pIn->metaBlkDepth; local in function:Addr::V2::Gfx9Lib::HwlComputeDccAddrFromCoord
1132 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
5092 UINT_32 zb = pIn->slice / localOut.blockSlices + + mipStartPos.d; local in function:Addr::V2::Gfx9Lib::HwlComputeSurfaceAddrFromCoordTiled
5097 UINT_64 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface_meta_address_test.c83 unsigned zb = z >> meta_block_depth_log2; local in function:gfx9_meta_addr_from_coord
85 unsigned blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
H A Dac_surface.c3093 nir_ssa_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2); local in function:gfx9_nir_meta_addr_from_coord
3095 nir_ssa_def *blockIndex = nir_iadd(b, nir_iadd(b, nir_imul(b, zb, sliceSizeInBlock),
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/panfrost/
H A Dpan_context.c2126 struct pipe_surface *zb = fb->zsbuf; local in function:panfrost_set_framebuffer_state
2128 if (ctx->pipe_framebuffer.zsbuf != zb) {
2129 pipe_surface_reference(&ctx->pipe_framebuffer.zsbuf, zb);
2131 if (zb) {
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Devergreen_state.c1918 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; local in function:evergreen_emit_framebuffer_state
1923 zb->base.texture->nr_samples > 1 ?
1927 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1930 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1931 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1932 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1933 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1934 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1935 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1936 radeon_emit(cs, zb
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Devergreen_state.c1924 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; local in function:evergreen_emit_framebuffer_state
1929 zb->base.texture->nr_samples > 1 ?
1933 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1936 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1937 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1938 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1939 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1940 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1941 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1942 radeon_emit(cs, zb
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