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    Searched defs:Intr (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptimizeSZextends.cpp 119 Value *Intr = Shl->getOperand(0);
127 if (IntrinsicInst *I = dyn_cast<IntrinsicInst>(Intr)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstrInfo.h 38 unsigned Intr;
42 const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
45 unsigned Intr;
48 const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
51 unsigned Intr;
77 const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
AMDGPUInstCombineIntrinsic.cpp 31 unsigned Intr;
AMDGPUPromoteAlloca.cpp 1004 IntrinsicInst *Intr = cast<IntrinsicInst>(Call);
1005 Builder.SetInsertPoint(Intr);
1006 switch (Intr->getIntrinsicID()) {
1010 Intr->eraseFromParent();
1017 DeferredIntrs.push_back(Intr);
1020 MemSetInst *MemSet = cast<MemSetInst>(Intr);
1024 Intr->eraseFromParent();
1031 Intr->eraseFromParent();
1037 Value *Src = Intr->getOperand(0);
1041 { Intr->getType(), PointerType::get(SrcTy, AMDGPUAS::LOCAL_ADDRESS)
    [all...]
AMDGPUInstructionSelector.cpp 1465 MachineInstr &MI, const AMDGPU::ImageDimIntrinsicInfo *Intr) const {
1470 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1472 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
1474 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
1476 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
1477 unsigned IntrOpcode = Intr->BaseOpcode;
1491 Unorm = MI.getOperand(ArgOffset + Intr->UnormIndex).getImm() != 0;
1496 if (!parseTexFail(MI.getOperand(ArgOffset + Intr->TexFailCtrlIndex).getImm(),
1500 const int Flags = MI.getOperand(ArgOffset + Intr->NumArgs).getImm();
1531 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm()
    [all...]
SIISelLowering.cpp 1043 const AMDGPU::ImageDimIntrinsicInfo *Intr
1046 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
4919 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4920 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4921 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
4974 SDNode *Intr = BRCOND.getOperand(1).getNode();
4979 if (Intr->getOpcode() == ISD::SETCC) {
4981 SetCC = Intr;
4982 Intr = SetCC->getOperand(0).getNode();
4991 unsigned CFNode = isCFIntrinsic(Intr);
    [all...]
  /src/sys/dev/ppbus/
ppbus_1284.h 70 #define Intr nACK
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
SearchableTableEmitter.cpp 146 std::unique_ptr<CodeGenIntrinsic> &Intr = Intrinsics[I];
147 if (!Intr)
148 Intr = std::make_unique<CodeGenIntrinsic>(cast<DefInit>(I)->getDef(),
150 return *Intr;
  /src/external/apache2/llvm/dist/clang/utils/TableGen/
NeonEmitter.cpp 514 Intrinsic &Intr;
518 DagEmitter(Intrinsic &Intr, StringRef CallPrefix) :
519 Intr(Intr), CallPrefix(CallPrefix) {
1467 if (Intr.getRecord()->getValueAsBit("isLaneQ"))
1469 MangledName = Intr.mangleName(N, ClassS);
1471 Intrinsic &Callee = Intr.Emitter.getIntrinsic(N, Types, MangledName);
1475 Intr.Dependencies.insert(&Callee);
1509 assert_with_loc(Intr.Variables.find(std::string(
1510 DI->getArgNameStr(ArgIdx))) != Intr.Variables.end()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 2293 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2315 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2316 switch (Intr) {
2363 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2367 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2390 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2391 switch (Intr) {
2398 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
WholeProgramDevirt.cpp 1292 Function *Intr =
1295 auto *CI = CallInst::Create(Intr, JTArgs, "", BB);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 1950 Function *Intr = Intrinsic::getDeclaration(F->getParent(),
1952 Elt0 = Builder.CreateCall(Intr, Elt0);
2336 Function *Intr = Intrinsic::getDeclaration(F->getParent(), IID, ResultTy);
2337 Rep = Builder.CreateCall(Intr, { CI->getOperand(0), CI->getOperand(1),
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 2005 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
2007 SDValue NewChain = SDValue(Intr.getNode(), 1);
2009 return Intr.getNode();
2022 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), Op->getVTList(), Ops);
2023 return Intr.getNode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 14970 Intrinsic::ID Intr, IntrLD, IntrPerm;
14972 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr
14980 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
15066 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
15068 if (IID == Intr && N->getOperand(1)->getOpcode() == ISD::ADD) {

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