| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CodeGenTypeCache.h | 39 llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy;
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| CGBuiltin.cpp | 5294 return llvm::FixedVectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad));
5320 return llvm::FixedVectorType::get(CGF->HalfTy, (4 << IsQuad));
6458 Ty = HalfTy;
6980 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16);
6987 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16);
6994 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16);
7001 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16);
9723 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::fabs, HalfTy), Ops, "vabs");
9769 llvm::Type *FTy = HalfTy;
9794 llvm::Type* FTy = HalfTy;
[all...] |
| ItaniumCXXABI.cpp | 4167 getContext().UnsignedInt128Ty, getContext().HalfTy,
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| CodeGenModule.cpp | 115 HalfTy = llvm::Type::getHalfTy(LLVMContext);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterBankInfo.h | 127 LLT HalfTy,
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| AMDGPURegisterBankInfo.cpp | 648 LLT HalfTy,
650 assert(HalfTy.getSizeInBits() == 32);
652 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy);
653 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy);
2192 LLT HalfTy = getHalfSizedType(DstTy);
2205 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2207 setRegsToType(MRI, Src1Regs, HalfTy);
2211 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg());
2213 setRegsToType(MRI, Src2Regs, HalfTy);
2215 setRegsToType(MRI, DefRegs, HalfTy);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| LLVMContextImpl.cpp | 28 HalfTy(C, Type::HalfTyID),
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| Type.cpp | 182 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; }
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| LLVMContextImpl.h | 1429 Type VoidTy, LabelTy, HalfTy, BFloatTy, FloatTy, DoubleTy, MetadataTy,
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| CombinerHelper.cpp | 2204 LLT HalfTy = LLT::scalar(HalfSize);
2207 auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg);
2219 Narrowed = Builder.buildLShr(HalfTy, Narrowed,
2220 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
2223 auto Zero = Builder.buildConstant(HalfTy, 0);
2232 Narrowed = Builder.buildShl(HalfTy, Narrowed,
2233 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
2236 auto Zero = Builder.buildConstant(HalfTy, 0);
2241 HalfTy, Unmerge.getReg(1),
2242 Builder.buildConstant(HalfTy, HalfSize - 1))
[all...] |
| LegalizerHelper.cpp | 4350 const LLT HalfTy, const LLT AmtTy) {
4352 Register InL = MRI.createGenericVirtualRegister(HalfTy);
4353 Register InH = MRI.createGenericVirtualRegister(HalfTy);
4362 LLT NVT = HalfTy;
4363 unsigned NVTBits = HalfTy.getSizeInBits();
4462 const LLT HalfTy = LLT::scalar(NewBitSize);
4468 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
4476 Register InL = MRI.createGenericVirtualRegister(HalfTy);
4477 Register InH = MRI.createGenericVirtualRegister(HalfTy);
4491 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizerHelper.h | 324 LLT HalfTy, LLT ShiftAmtTy);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 336 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2);
337 return { HalfTy, HalfTy };
1318 MVT HalfTy = typeSplit(VecTy).first;
1319 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy,
1321 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy,
1795 MVT HalfTy = typeSplit(ResTy).first;
1796 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL);
1797 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH);
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| HexagonISelDAGToDAGHVX.cpp | 992 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(),
996 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op);
1148 MVT HalfTy = getSingleVT(MVT::i8);
1151 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) };
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| HexagonISelLowering.cpp | 2490 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2493 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2496 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
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| /src/external/apache2/llvm/dist/clang/lib/AST/ |
| PrintfFormatString.cpp | 580 return Ctx.HalfTy;
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| ASTContext.cpp | 1478 InitBuiltinType(HalfTy, BuiltinType::Half);
3819 return SVE_ELTTY(HalfTy, 8, 1);
3821 return SVE_ELTTY(HalfTy, 8, 2);
3823 return SVE_ELTTY(HalfTy, 8, 3);
3825 return SVE_ELTTY(HalfTy, 8, 4);
3857 return {ElBits == 16 ? HalfTy : (ElBits == 32 ? FloatTy : DoubleTy), \
6265 case Float16Rank: return HalfTy;
6267 case HalfRank: return HalfTy;
10369 Type = Context.HalfTy;
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| /src/external/apache2/llvm/dist/clang/include/clang/AST/ |
| ASTContext.h | 1025 CanQualType HalfTy; // [OpenCL 6.1.1.1], ARM NEON
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| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaExpr.cpp | 3820 Ty = Context.HalfTy;
13878 assert((isVector(ResultTy, Context.HalfTy) ||
13881 assert(isVector(LHS.get()->getType(), Context.HalfTy) &&
13882 isVector(RHS.get()->getType(), Context.HalfTy) &&
13944 return VT->getElementType().getCanonicalType() == Ctx.HalfTy;
14166 (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) ==
14167 isVector(LHS.get()->getType(), Context.HalfTy)) &&
14863 return convertVector(UO, Context.HalfTy, *this);
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| SemaChecking.cpp | 2076 return Context.HalfTy;
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| SemaType.cpp | 1518 case DeclSpec::TST_half: Result = Context.HalfTy; break;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 11107 auto *HalfTy = HalfV->getType();
11109 2 * HalfTy->getPrimitiveSizeInBits().getFixedSize();
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| /src/external/apache2/llvm/dist/clang/lib/Serialization/ |
| ASTReader.cpp | 6876 T = Context.HalfTy;
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